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@@ -0,0 +1,579 @@
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+/*
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+ * Device Tree Source for AMCC Glacier (460GT)
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+ *
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+ * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
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+ *
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+ * SPDX-License-Identifier: GPL-2.0
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+ */
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+
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+/dts-v1/;
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+
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+/ {
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+ #address-cells = <2>;
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+ #size-cells = <1>;
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+ model = "amcc,glacier";
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+ compatible = "amcc,glacier";
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+ dcr-parent = <&{/cpus/cpu@0}>;
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+
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+ aliases {
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+ ethernet0 = &EMAC0;
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+ ethernet1 = &EMAC1;
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+ ethernet2 = &EMAC2;
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+ ethernet3 = &EMAC3;
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+ serial0 = &UART0;
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+ serial1 = &UART1;
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+ };
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+
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+ chosen {
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+ stdout-path = &UART0;
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+ };
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+
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ cpu@0 {
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+ device_type = "cpu";
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+ model = "PowerPC,460GT";
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+ reg = <0x00000000>;
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+ clock-frequency = <0>; /* Filled in by U-Boot */
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+ timebase-frequency = <0>; /* Filled in by U-Boot */
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+ i-cache-line-size = <32>;
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+ d-cache-line-size = <32>;
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+ i-cache-size = <32768>;
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+ d-cache-size = <32768>;
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+ dcr-controller;
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+ dcr-access-method = "native";
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+ next-level-cache = <&L2C0>;
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+ };
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+ };
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+
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+ memory {
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+ device_type = "memory";
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+ reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
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+ };
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+
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+ UIC0: interrupt-controller0 {
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+ compatible = "ibm,uic-460gt","ibm,uic";
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+ interrupt-controller;
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+ cell-index = <0>;
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+ dcr-reg = <0x0c0 0x009>;
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+ #address-cells = <0>;
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+ #size-cells = <0>;
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+ #interrupt-cells = <2>;
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+ };
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+
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+ UIC1: interrupt-controller1 {
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+ compatible = "ibm,uic-460gt","ibm,uic";
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+ interrupt-controller;
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+ cell-index = <1>;
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+ dcr-reg = <0x0d0 0x009>;
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+ #address-cells = <0>;
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+ #size-cells = <0>;
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+ #interrupt-cells = <2>;
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+ interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
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+ interrupt-parent = <&UIC0>;
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+ };
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+
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+ UIC2: interrupt-controller2 {
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+ compatible = "ibm,uic-460gt","ibm,uic";
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+ interrupt-controller;
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+ cell-index = <2>;
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+ dcr-reg = <0x0e0 0x009>;
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+ #address-cells = <0>;
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+ #size-cells = <0>;
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+ #interrupt-cells = <2>;
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+ interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
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+ interrupt-parent = <&UIC0>;
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+ };
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+
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+ UIC3: interrupt-controller3 {
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+ compatible = "ibm,uic-460gt","ibm,uic";
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+ interrupt-controller;
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+ cell-index = <3>;
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+ dcr-reg = <0x0f0 0x009>;
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+ #address-cells = <0>;
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+ #size-cells = <0>;
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+ #interrupt-cells = <2>;
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+ interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
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+ interrupt-parent = <&UIC0>;
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+ };
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+
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+ SDR0: sdr {
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+ compatible = "ibm,sdr-460gt";
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+ dcr-reg = <0x00e 0x002>;
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+ };
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+
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+ CPR0: cpr {
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+ compatible = "ibm,cpr-460gt";
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+ dcr-reg = <0x00c 0x002>;
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+ };
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+
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+ L2C0: l2c {
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+ compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
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+ dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
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+ 0x030 0x008>; /* L2 cache DCR's */
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+ cache-line-size = <32>; /* 32 bytes */
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+ cache-size = <262144>; /* L2, 256K */
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+ interrupt-parent = <&UIC1>;
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+ interrupts = <11 1>;
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+ };
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+
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+ plb {
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+ compatible = "ibm,plb-460gt", "ibm,plb4";
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+ #address-cells = <2>;
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+ #size-cells = <1>;
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+ ranges;
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+ clock-frequency = <0>; /* Filled in by U-Boot */
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+
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+ SDRAM0: sdram {
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+ compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
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+ dcr-reg = <0x010 0x002>;
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+ };
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+
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+ CRYPTO: crypto@180000 {
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+ compatible = "amcc,ppc460gt-crypto", "amcc,ppc460ex-crypto",
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+ "amcc,ppc4xx-crypto";
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+ reg = <4 0x00180000 0x80400>;
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+ interrupt-parent = <&UIC0>;
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+ interrupts = <0x1d 0x4>;
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+ };
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+
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+ HWRNG: hwrng@110000 {
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+ compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
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+ reg = <4 0x00110000 0x50>;
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+ };
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+
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+ MAL0: mcmal {
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+ compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
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+ dcr-reg = <0x180 0x062>;
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+ num-tx-chans = <4>;
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+ num-rx-chans = <32>;
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+ #address-cells = <0>;
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+ #size-cells = <0>;
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+ interrupt-parent = <&UIC2>;
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+ interrupts = < /*TXEOB*/ 0x6 0x4
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+ /*RXEOB*/ 0x7 0x4
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+ /*SERR*/ 0x3 0x4
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+ /*TXDE*/ 0x4 0x4
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+ /*RXDE*/ 0x5 0x4>;
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+ desc-base-addr-high = <0x8>;
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+ };
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+
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+ POB0: opb {
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+ compatible = "ibm,opb-460gt", "ibm,opb";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
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+ clock-frequency = <0>; /* Filled in by U-Boot */
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+
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+ EBC0: ebc {
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+ compatible = "ibm,ebc-460gt", "ibm,ebc";
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+ dcr-reg = <0x012 0x002>;
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+ #address-cells = <2>;
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+ #size-cells = <1>;
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+ clock-frequency = <0>; /* Filled in by U-Boot */
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+ /* ranges property is supplied by U-Boot */
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+ interrupts = <0x6 0x4>;
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+ interrupt-parent = <&UIC1>;
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+
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+ nor_flash@0,0 {
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+ compatible = "amd,s29gl512n", "cfi-flash";
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+ bank-width = <2>;
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+ reg = <0x00000000 0x00000000 0x04000000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ partition@0 {
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+ label = "kernel";
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+ reg = <0x00000000 0x001e0000>;
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+ };
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+ partition@1e0000 {
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+ label = "dtb";
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+ reg = <0x001e0000 0x00020000>;
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+ };
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+ partition@200000 {
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+ label = "ramdisk";
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+ reg = <0x00200000 0x01400000>;
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+ };
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+ partition@1600000 {
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+ label = "jffs2";
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+ reg = <0x01600000 0x00400000>;
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+ };
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+ partition@1a00000 {
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+ label = "user";
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+ reg = <0x01a00000 0x02560000>;
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+ };
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+ partition@3f60000 {
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+ label = "env";
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+ reg = <0x03f60000 0x00040000>;
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+ };
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+ partition@3fa0000 {
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+ label = "u-boot";
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+ reg = <0x03fa0000 0x00060000>;
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+ };
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+ };
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+
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+ ndfc@3,0 {
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+ compatible = "ibm,ndfc";
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+ reg = <0x00000003 0x00000000 0x00002000>;
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+ ccr = <0x00001000>;
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+ bank-settings = <0x80002222>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ nand {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ partition@0 {
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+ label = "u-boot";
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+ reg = <0x00000000 0x00100000>;
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+ };
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+ partition@100000 {
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+ label = "user";
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+ reg = <0x00000000 0x03f00000>;
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+ };
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+ };
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+ };
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+ };
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+
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+ UART0: serial@ef600300 {
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+ device_type = "serial";
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+ reg-shift = <0>;
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+ compatible = "ns16550";
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+ reg = <0xef600300 0x00000008>;
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+ virtual-reg = <0xef600300>;
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+ clock-frequency = <0>; /* Filled in by U-Boot */
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+ current-speed = <0>; /* Filled in by U-Boot */
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+ interrupt-parent = <&UIC1>;
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+ interrupts = <0x1 0x4>;
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+ };
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+
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+ UART1: serial@ef600400 {
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+ device_type = "serial";
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+ compatible = "ns16550";
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+ reg = <0xef600400 0x00000008>;
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+ virtual-reg = <0xef600400>;
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+ clock-frequency = <0>; /* Filled in by U-Boot */
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+ current-speed = <0>; /* Filled in by U-Boot */
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+ interrupt-parent = <&UIC0>;
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+ interrupts = <0x1 0x4>;
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+ };
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+
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+ UART2: serial@ef600500 {
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+ device_type = "serial";
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+ compatible = "ns16550";
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+ reg = <0xef600500 0x00000008>;
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+ virtual-reg = <0xef600500>;
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+ clock-frequency = <0>; /* Filled in by U-Boot */
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+ current-speed = <0>; /* Filled in by U-Boot */
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+ interrupt-parent = <&UIC1>;
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+ interrupts = <28 0x4>;
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+ };
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+
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+ UART3: serial@ef600600 {
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+ device_type = "serial";
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+ compatible = "ns16550";
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+ reg = <0xef600600 0x00000008>;
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+ virtual-reg = <0xef600600>;
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+ clock-frequency = <0>; /* Filled in by U-Boot */
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+ current-speed = <0>; /* Filled in by U-Boot */
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+ interrupt-parent = <&UIC1>;
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+ interrupts = <29 0x4>;
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+ };
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+
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+ IIC0: i2c@ef600700 {
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+ compatible = "ibm,iic-460gt", "ibm,iic";
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+ reg = <0xef600700 0x00000014>;
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+ interrupt-parent = <&UIC0>;
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+ interrupts = <0x2 0x4>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ rtc@68 {
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+ compatible = "stm,m41t80";
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+ reg = <0x68>;
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+ interrupt-parent = <&UIC2>;
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+ interrupts = <0x19 0x8>;
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+ };
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+ sttm@48 {
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+ compatible = "ad,ad7414";
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+ reg = <0x48>;
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+ interrupt-parent = <&UIC1>;
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+ interrupts = <0x14 0x8>;
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+ };
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+ };
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+
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+ IIC1: i2c@ef600800 {
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+ compatible = "ibm,iic-460gt", "ibm,iic";
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+ reg = <0xef600800 0x00000014>;
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+ interrupt-parent = <&UIC0>;
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+ interrupts = <0x3 0x4>;
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+ };
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+
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+ ZMII0: emac-zmii@ef600d00 {
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+ compatible = "ibm,zmii-460gt", "ibm,zmii";
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+ reg = <0xef600d00 0x0000000c>;
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+ };
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+
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+ RGMII0: emac-rgmii@ef601500 {
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+ compatible = "ibm,rgmii-460gt", "ibm,rgmii";
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+ reg = <0xef601500 0x00000008>;
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+ has-mdio;
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+ };
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+
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+ RGMII1: emac-rgmii@ef601600 {
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+ compatible = "ibm,rgmii-460gt", "ibm,rgmii";
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+ reg = <0xef601600 0x00000008>;
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+ has-mdio;
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+ };
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+
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+ TAH0: emac-tah@ef601350 {
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+ compatible = "ibm,tah-460gt", "ibm,tah";
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+ reg = <0xef601350 0x00000030>;
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+ };
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+
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+ TAH1: emac-tah@ef601450 {
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+ compatible = "ibm,tah-460gt", "ibm,tah";
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+ reg = <0xef601450 0x00000030>;
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+ };
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+
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+ EMAC0: ethernet@ef600e00 {
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+ device_type = "network";
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+ compatible = "ibm,emac-460gt", "ibm,emac4sync";
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+ interrupt-parent = <&EMAC0>;
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+ interrupts = <0x0 0x1>;
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+ #interrupt-cells = <1>;
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+ #address-cells = <0>;
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+ #size-cells = <0>;
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+ interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
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+ /*Wake*/ 0x1 &UIC2 0x14 0x4>;
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+ reg = <0xef600e00 0x000000c4>;
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+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
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+ mal-device = <&MAL0>;
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+ mal-tx-channel = <0>;
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+ mal-rx-channel = <0>;
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+ cell-index = <0>;
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+ max-frame-size = <9000>;
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+ rx-fifo-size = <4096>;
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+ tx-fifo-size = <2048>;
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+ rx-fifo-size-gige = <16384>;
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+ phy-mode = "rgmii";
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+ phy-map = <0x00000000>;
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+ rgmii-device = <&RGMII0>;
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+ rgmii-channel = <0>;
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+ tah-device = <&TAH0>;
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+ tah-channel = <0>;
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+ has-inverted-stacr-oc;
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+ has-new-stacr-staopc;
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+ };
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+
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+ EMAC1: ethernet@ef600f00 {
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+ device_type = "network";
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+ compatible = "ibm,emac-460gt", "ibm,emac4sync";
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+ interrupt-parent = <&EMAC1>;
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+ interrupts = <0x0 0x1>;
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+ #interrupt-cells = <1>;
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+ #address-cells = <0>;
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+ #size-cells = <0>;
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+ interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
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+ /*Wake*/ 0x1 &UIC2 0x15 0x4>;
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+ reg = <0xef600f00 0x000000c4>;
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+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
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+ mal-device = <&MAL0>;
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+ mal-tx-channel = <1>;
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+ mal-rx-channel = <8>;
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+ cell-index = <1>;
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+ max-frame-size = <9000>;
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+ rx-fifo-size = <4096>;
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+ tx-fifo-size = <2048>;
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+ rx-fifo-size-gige = <16384>;
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+ phy-mode = "rgmii";
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+ phy-map = <0x00000000>;
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+ rgmii-device = <&RGMII0>;
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+ rgmii-channel = <1>;
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+ tah-device = <&TAH1>;
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+ tah-channel = <1>;
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+ has-inverted-stacr-oc;
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|
+ has-new-stacr-staopc;
|
|
|
+ mdio-device = <&EMAC0>;
|
|
|
+ };
|
|
|
+
|
|
|
+ EMAC2: ethernet@ef601100 {
|
|
|
+ device_type = "network";
|
|
|
+ compatible = "ibm,emac-460gt", "ibm,emac4sync";
|
|
|
+ interrupt-parent = <&EMAC2>;
|
|
|
+ interrupts = <0x0 0x1>;
|
|
|
+ #interrupt-cells = <1>;
|
|
|
+ #address-cells = <0>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
|
|
|
+ /*Wake*/ 0x1 &UIC2 0x16 0x4>;
|
|
|
+ reg = <0xef601100 0x000000c4>;
|
|
|
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
|
|
+ mal-device = <&MAL0>;
|
|
|
+ mal-tx-channel = <2>;
|
|
|
+ mal-rx-channel = <16>;
|
|
|
+ cell-index = <2>;
|
|
|
+ max-frame-size = <9000>;
|
|
|
+ rx-fifo-size = <4096>;
|
|
|
+ tx-fifo-size = <2048>;
|
|
|
+ rx-fifo-size-gige = <16384>;
|
|
|
+ tx-fifo-size-gige = <16384>; /* emac2&3 only */
|
|
|
+ phy-mode = "rgmii";
|
|
|
+ phy-map = <0x00000000>;
|
|
|
+ rgmii-device = <&RGMII1>;
|
|
|
+ rgmii-channel = <0>;
|
|
|
+ has-inverted-stacr-oc;
|
|
|
+ has-new-stacr-staopc;
|
|
|
+ mdio-device = <&EMAC0>;
|
|
|
+ };
|
|
|
+
|
|
|
+ EMAC3: ethernet@ef601200 {
|
|
|
+ device_type = "network";
|
|
|
+ compatible = "ibm,emac-460gt", "ibm,emac4sync";
|
|
|
+ interrupt-parent = <&EMAC3>;
|
|
|
+ interrupts = <0x0 0x1>;
|
|
|
+ #interrupt-cells = <1>;
|
|
|
+ #address-cells = <0>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4
|
|
|
+ /*Wake*/ 0x1 &UIC2 0x17 0x4>;
|
|
|
+ reg = <0xef601200 0x000000c4>;
|
|
|
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
|
|
+ mal-device = <&MAL0>;
|
|
|
+ mal-tx-channel = <3>;
|
|
|
+ mal-rx-channel = <24>;
|
|
|
+ cell-index = <3>;
|
|
|
+ max-frame-size = <9000>;
|
|
|
+ rx-fifo-size = <4096>;
|
|
|
+ tx-fifo-size = <2048>;
|
|
|
+ rx-fifo-size-gige = <16384>;
|
|
|
+ tx-fifo-size-gige = <16384>; /* emac2&3 only */
|
|
|
+ phy-mode = "rgmii";
|
|
|
+ phy-map = <0x00000000>;
|
|
|
+ rgmii-device = <&RGMII1>;
|
|
|
+ rgmii-channel = <1>;
|
|
|
+ has-inverted-stacr-oc;
|
|
|
+ has-new-stacr-staopc;
|
|
|
+ mdio-device = <&EMAC0>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ PCIX0: pci@c0ec00000 {
|
|
|
+ device_type = "pci";
|
|
|
+ #interrupt-cells = <1>;
|
|
|
+ #size-cells = <2>;
|
|
|
+ #address-cells = <3>;
|
|
|
+ compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix";
|
|
|
+ primary;
|
|
|
+ large-inbound-windows;
|
|
|
+ enable-msi-hole;
|
|
|
+ reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
|
|
|
+ 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
|
|
|
+ 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
|
|
|
+ 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
|
|
|
+ 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
|
|
|
+
|
|
|
+ /* Outbound ranges, one memory and one IO,
|
|
|
+ * later cannot be changed
|
|
|
+ */
|
|
|
+ ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
|
|
|
+ 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
|
|
|
+ 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
|
|
|
+
|
|
|
+ /* Inbound 2GB range starting at 0 */
|
|
|
+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
|
|
+
|
|
|
+ /* This drives busses 0 to 0x3f */
|
|
|
+ bus-range = <0x0 0x3f>;
|
|
|
+
|
|
|
+ /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
|
|
|
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
|
|
|
+ interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
|
|
|
+ };
|
|
|
+
|
|
|
+ PCIE0: pciex@d00000000 {
|
|
|
+ device_type = "pci";
|
|
|
+ #interrupt-cells = <1>;
|
|
|
+ #size-cells = <2>;
|
|
|
+ #address-cells = <3>;
|
|
|
+ compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
|
|
|
+ primary;
|
|
|
+ port = <0x0>; /* port number */
|
|
|
+ reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
|
|
|
+ 0x0000000c 0x08010000 0x00001000>; /* Registers */
|
|
|
+ dcr-reg = <0x100 0x020>;
|
|
|
+ sdr-base = <0x300>;
|
|
|
+
|
|
|
+ /* Outbound ranges, one memory and one IO,
|
|
|
+ * later cannot be changed
|
|
|
+ */
|
|
|
+ ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
|
|
|
+ 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
|
|
|
+ 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
|
|
|
+
|
|
|
+ /* Inbound 2GB range starting at 0 */
|
|
|
+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
|
|
+
|
|
|
+ /* This drives busses 40 to 0x7f */
|
|
|
+ bus-range = <0x40 0x7f>;
|
|
|
+
|
|
|
+ /* Legacy interrupts (note the weird polarity, the bridge seems
|
|
|
+ * to invert PCIe legacy interrupts).
|
|
|
+ * We are de-swizzling here because the numbers are actually for
|
|
|
+ * port of the root complex virtual P2P bridge. But I want
|
|
|
+ * to avoid putting a node for it in the tree, so the numbers
|
|
|
+ * below are basically de-swizzled numbers.
|
|
|
+ * The real slot is on idsel 0, so the swizzling is 1:1
|
|
|
+ */
|
|
|
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
|
|
+ interrupt-map = <
|
|
|
+ 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
|
|
|
+ 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
|
|
|
+ 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
|
|
|
+ 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
|
|
|
+ };
|
|
|
+
|
|
|
+ PCIE1: pciex@d20000000 {
|
|
|
+ device_type = "pci";
|
|
|
+ #interrupt-cells = <1>;
|
|
|
+ #size-cells = <2>;
|
|
|
+ #address-cells = <3>;
|
|
|
+ compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
|
|
|
+ primary;
|
|
|
+ port = <0x1>; /* port number */
|
|
|
+ reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
|
|
|
+ 0x0000000c 0x08011000 0x00001000>; /* Registers */
|
|
|
+ dcr-reg = <0x120 0x020>;
|
|
|
+ sdr-base = <0x340>;
|
|
|
+
|
|
|
+ /* Outbound ranges, one memory and one IO,
|
|
|
+ * later cannot be changed
|
|
|
+ */
|
|
|
+ ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
|
|
|
+ 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
|
|
|
+ 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
|
|
|
+
|
|
|
+ /* Inbound 2GB range starting at 0 */
|
|
|
+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
|
|
|
+
|
|
|
+ /* This drives busses 80 to 0xbf */
|
|
|
+ bus-range = <0x80 0xbf>;
|
|
|
+
|
|
|
+ /* Legacy interrupts (note the weird polarity, the bridge seems
|
|
|
+ * to invert PCIe legacy interrupts).
|
|
|
+ * We are de-swizzling here because the numbers are actually for
|
|
|
+ * port of the root complex virtual P2P bridge. But I want
|
|
|
+ * to avoid putting a node for it in the tree, so the numbers
|
|
|
+ * below are basically de-swizzled numbers.
|
|
|
+ * The real slot is on idsel 0, so the swizzling is 1:1
|
|
|
+ */
|
|
|
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
|
|
+ interrupt-map = <
|
|
|
+ 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
|
|
|
+ 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
|
|
|
+ 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
|
|
|
+ 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+};
|
Simon Glass