Merge git://git.denx.de/u-boot-fsl-qoriq

arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -72,6 +72,7 @@ config ARCH_LS1088A
 	select SYS_FSL_ERRATUM_A010165
 	select SYS_FSL_ERRATUM_A008511
 	select SYS_FSL_ERRATUM_A008850
+	select SYS_FSL_ERRATUM_A009007
 	select SYS_FSL_HAS_CCI400
 	select SYS_FSL_HAS_DDR4
 	select SYS_FSL_HAS_RGMII

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -647,13 +647,14 @@ phys_size_t get_effective_memsize(void)
 
 	/*
 	 * For ARMv8 SoCs, DDR memory is split into two or three regions. The
-	 * first region is 2GB space at 0x8000_0000. If the memory extends to
-	 * the second region (or the third region if applicable), the secure
-	 * memory and Management Complex (MC) memory should be put into the
-	 * highest region, i.e. the end of DDR memory. CONFIG_MAX_MEM_MAPPED
-	 * is set to the size of first region so U-Boot doesn't relocate itself
-	 * into higher address. Should DDR be configured to skip the first
-	 * region, this function needs to be adjusted.
+	 * first region is 2GB space at 0x8000_0000. Secure memory needs to
+	 * allocated from first region. If the memory extends to  the second
+	 * region (or the third region if applicable), Management Complex (MC)
+	 * memory should be put into the highest region, i.e. the end of DDR
+	 * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
+	 * U-Boot doesn't relocate itself into higher address. Should DDR be
+	 * configured to skip the first region, this function needs to be
+	 * adjusted.
 	 */
 	if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
 		ea_size = CONFIG_MAX_MEM_MAPPED;
@@ -664,16 +665,10 @@ phys_size_t get_effective_memsize(void)
 
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 	/* Check if we have enough space for secure memory */
-	if (rem > CONFIG_SYS_MEM_RESERVE_SECURE) {
-		rem -= CONFIG_SYS_MEM_RESERVE_SECURE;
-	} else {
-		if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE) {
-			ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
-			rem = 0;	/* Presume MC requires more memory */
-		} else {
-			printf("Error: No enough space for secure memory.\n");
-		}
-	}
+	if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
+		ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
+	else
+		printf("Error: No enough space for secure memory.\n");
 #endif
 	/* Check if we have enough memory for MC */
 	if (rem < board_reserve_ram_top(rem)) {
@@ -698,8 +693,19 @@ int dram_init_banksize(void)
 	 * memory. The DDR extends from low region to high region(s) presuming
 	 * no hole is created with DDR configuration. gd->arch.secure_ram tracks
 	 * the location of secure memory. gd->arch.resv_ram tracks the location
-	 * of reserved memory for Management Complex (MC).
+	 * of reserved memory for Management Complex (MC). Because gd->ram_size
+	 * is reduced by this function if secure memory is reserved, checking
+	 * gd->arch.secure_ram should be done to avoid running it repeatedly.
 	 */
+
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+	if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
+		debug("No need to run again, skip %s\n", __func__);
+
+		return 0;
+	}
+#endif
+
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
 		gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
@@ -718,32 +724,14 @@ int dram_init_banksize(void)
 		gd->bd->bi_dram[0].size = gd->ram_size;
 	}
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
-	if (gd->bd->bi_dram[2].size >= CONFIG_SYS_MEM_RESERVE_SECURE) {
-		gd->bd->bi_dram[2].size -= CONFIG_SYS_MEM_RESERVE_SECURE;
-		gd->arch.secure_ram = gd->bd->bi_dram[2].start +
-				      gd->bd->bi_dram[2].size;
+	if (gd->bd->bi_dram[0].size >
+				CONFIG_SYS_MEM_RESERVE_SECURE) {
+		gd->bd->bi_dram[0].size -=
+				CONFIG_SYS_MEM_RESERVE_SECURE;
+		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+				      gd->bd->bi_dram[0].size;
 		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 		gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
-	} else
-#endif
-	{
-		if (gd->bd->bi_dram[1].size >= CONFIG_SYS_MEM_RESERVE_SECURE) {
-			gd->bd->bi_dram[1].size -=
-					CONFIG_SYS_MEM_RESERVE_SECURE;
-			gd->arch.secure_ram = gd->bd->bi_dram[1].start +
-					      gd->bd->bi_dram[1].size;
-			gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-			gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
-		} else if (gd->bd->bi_dram[0].size >
-					CONFIG_SYS_MEM_RESERVE_SECURE) {
-			gd->bd->bi_dram[0].size -=
-					CONFIG_SYS_MEM_RESERVE_SECURE;
-			gd->arch.secure_ram = gd->bd->bi_dram[0].start +
-					      gd->bd->bi_dram[0].size;
-			gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-			gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
-		}
 	}
 #endif	/* CONFIG_SYS_MEM_RESERVE_SECURE */
 
@@ -797,6 +785,11 @@ int dram_init_banksize(void)
 	}
 #endif
 
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+	debug("%s is called. gd->ram_size is reduced to %lu\n",
+	      __func__, (ulong)gd->ram_size);
+#endif
+
 	return 0;
 }
 

arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon

@@ -0,0 +1,140 @@
+Falcon boot option
+------------------
+Falcon boot is a short cut boot method for SD/eMMC targets. It skips loading the
+RAM version U-Boot. Instead, it loads FIT image and boot directly to Linux.
+CONFIG_SPL_OS_BOOT enables falcon boot. CONFIG_SPL_LOAD_FIT enables the FIT
+image support (also need CONFIG_SPL_OF_LIBFDT, CONFIG_SPL_FIT and optionally
+CONFIG_SPL_GZIP).
+
+To enable falcon boot, a hook function spl_start_uboot() returns 0 to indicate
+booting U-Boot is not the first choice. The kernel FIT image needs to be put
+at CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR. SPL mmc driver reads the header to
+determine if this is a FIT image. If true, FIT image components are parsed and
+copied or decompressed (if applicable) to their destinations. If FIT image is
+not found, normal U-Boot flow will follow.
+
+An important part of falcon boot is to prepare the device tree. A normal U-Boot
+does FDT fixups when booting Linux. For falcon boot, Linux boots directly from
+SPL, skipping the normal U-Boot. The device tree has to be prepared in advance.
+A command "spl export" should be called under the normal RAM version U-Boot.
+It is equivalent to go through "bootm" step-by-step until device tree fixup is
+done. The device tree in memory is the one needed for falcon boot. Falcon boot
+flow suggests to save this image to SD/eMMC at the location pointed by macro
+CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR, with maximum size specified by macro
+CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS. However, when FIT image is used for
+Linux, the device tree stored in FIT image overwrites the memory loaded by spl
+driver from these sectors. We could change this loading order to favor the
+stored sectors. But when secure boot is enabled, these sectors are used for
+signature header and needs to be loaded before the FIT image. So it is important
+to understand the device tree in FIT image should be the one actually used, or
+leave it absent to favor the stored sectors. It is easier to deploy the FIT
+image with embedded static device tree to multiple boards.
+
+Macro CONFIG_SYS_SPL_ARGS_ADDR serves two purposes. One is the pointer to load
+the stored sectors to. Normally this is the static device tree. The second
+purpose is the memory location of signature header for secure boot. After the
+FIT image is loaded into memory, it is validated against the signature header
+before individual components are extracted (and optionally decompressed) into
+their final memory locations, respectively. After the validation, the header
+is no longer used. The static device tree is copied into this location. So
+this macro is passed as the location of device tree when booting Linux.
+
+Steps to prepare static device tree
+-----------------------------------
+To prepare the static device tree for Layerscape boards, it is important to
+understand the fixups in U-Boot. Memory size and location, as well as reserved
+memory blocks are added/updated. Ethernet MAC addressed are updated. FMan
+microcode (if used) is embedded in the device tree. Kernel command line and
+initrd information are embedded. Others including CPU status, boot method,
+Ethernet port status, etc. are also updated.
+
+Following normal booting process, all variables are set, all images are loaded
+before "bootm" command would be issued to boot, run command
+
+spl export fdt <address>
+
+where the address is the location of FIT image. U-Boot goes through the booting
+process as if "bootm start", "bootm loados", "bootm ramdisk"... commands but
+stops before "bootm go". There we have the fixed-up device tree in memory.
+We can check the device tree header by these commands
+
+fdt addr <fdt address>
+fdt header
+
+Where the fdt address is the device tree in memory. It is printed by U-Boot.
+It is useful to know the exact size. One way to extract this static device
+tree is to save it to eMMC/SD using command in U-Boot, and extract under Linux
+with these commands, repectively
+
+mmc write <address> <sector> <sectors>
+dd if=/dev/mmcblk0 of=<filename> bs=512 skip=<sector> count=<sectors>
+
+Note, U-Boot takes values as hexadecimals while Linux takes them as decimals by
+default. If using NAND or other storage, the commands are slightly different.
+When we have the static device tree image, we can re-make the FIT image with
+it. It is important to specify the load addresses in FIT image for every
+components. Otherwise U-Boot cannot load them correctly.
+
+Generate FIT image with static device tree
+------------------------------------------
+Example:
+
+/dts-v1/;
+
+/ {
+	description = "Image file for the LS1043A Linux Kernel";
+	#address-cells = <1>;
+
+	images {
+		kernel@1 {
+			description = "ARM64 Linux kernel";
+			data = /incbin/("./arch/arm64/boot/Image.gz");
+			type = "kernel";
+			arch = "arm64";
+			os = "linux";
+			compression = "gzip";
+			load = <0x80080000>;
+			entry = <0x80080000>;
+		};
+		fdt@1 {
+			description = "Flattened Device Tree blob";
+			data = /incbin/("./fsl-ls1043ardb-static.dtb");
+			type = "flat_dt";
+			arch = "arm64";
+			compression = "none";
+			load = <0x90000000>;
+		};
+		ramdisk@1 {
+			description = "LS1043 Ramdisk";
+                        data = /incbin/("./rootfs.cpio.gz");
+			type = "ramdisk";
+			arch = "arm64";
+			os = "linux";
+			compression = "gzip";
+			load = <0xa0000000>;
+		};
+	};
+
+	configurations {
+		default = "config@1";
+		config@1 {
+			description = "Boot Linux kernel";
+			kernel = "kernel@1";
+			fdt = "fdt@1";
+			ramdisk = "ramdisk@1";
+			loadables = "fdt", "ramdisk";
+		};
+	};
+};
+
+The "loadables" is not optional. It tells SPL which images to load into memory.
+
+Other things to consider
+-----------------------
+Falcon boot skips a lot of initialization in U-Boot. If Linux expects the
+hardware to be initialized by U-Boot, the related code should be ported to SPL
+build. For example, if Linux expect Ethernet PHY to be initialized in U-Boot
+(which is not a common case), the PHY initialization has to be included in
+falcon boot. This increases the SPL image size and should be handled carefully.
+If Linux has PHY driver enabled, it still depends on the correct MDIO bus setup
+in U-Boot. Normal U-Boot sets the MDC ratio to generate a proper clock signal.

arch/arm/cpu/armv8/fsl-layerscape/soc.c

@@ -127,7 +127,7 @@ static void erratum_a008997(void)
 	out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);	\
 	out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
 
-#elif defined(CONFIG_ARCH_LS2080A)
+#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
 
 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy)	\
 	out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
@@ -149,7 +149,7 @@ static void erratum_a009007(void)
 
 	usb_phy = (void __iomem *)SCFG_USB_PHY3;
 	PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
-#elif defined(CONFIG_ARCH_LS2080A)
+#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
 	void __iomem *dcsr = (void __iomem *)DCSR_BASE;
 
 	PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);

arch/arm/cpu/armv8/fsl-layerscape/spl.c

@@ -80,6 +80,7 @@ void board_init_f(ulong dummy)
 	get_clocks();
 
 	preloader_console_init();
+	spl_set_bd();
 
 #ifdef CONFIG_SPL_I2C_SUPPORT
 	i2c_init_all();
@@ -116,4 +117,29 @@ void board_init_f(ulong dummy)
 	gd->arch.tlb_allocated = gd->arch.tlb_addr;
 #endif	/* CONFIG_SPL_FSL_LS_PPA */
 }
+
+#ifdef CONFIG_SPL_OS_BOOT
+/*
+ * Return
+ * 0 if booting into OS is selected
+ * 1 if booting into U-Boot is selected
+ */
+int spl_start_uboot(void)
+{
+	env_init();
+	if (env_get_yesno("boot_os") != 0)
+		return 0;
+
+	return 1;
+}
+#endif	/* CONFIG_SPL_OS_BOOT */
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
 #endif /* CONFIG_SPL_BUILD */

arch/arm/include/asm/system.h

@@ -215,8 +215,8 @@ void __asm_switch_ttbr(u64 new_ttbr);
  * @entry_point: kernel entry point
  * @es_flag:     execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
  */
-void armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr,
-			 u64 arg4, u64 entry_point, u64 es_flag);
+void __noreturn armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr,
+				    u64 arg4, u64 entry_point, u64 es_flag);
 /*
  * Switch from EL2 to EL1 for ARMv8
  *

arch/arm/lib/spl.c

@@ -7,6 +7,7 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
+
 #include <common.h>
 #include <config.h>
 #include <spl.h>
@@ -47,6 +48,15 @@ void __weak board_init_f(ulong dummy)
  * image.
  */
 #ifdef CONFIG_SPL_OS_BOOT
+#ifdef CONFIG_ARM64
+void __noreturn jump_to_image_linux(struct spl_image_info *spl_image)
+{
+	debug("Entering kernel arg pointer: 0x%p\n", spl_image->arg);
+	cleanup_before_linux();
+	armv8_switch_to_el2((u64)spl_image->arg, 0, 0, 0,
+			    spl_image->entry_point, ES_TO_AARCH64);
+}
+#else
 void __noreturn jump_to_image_linux(struct spl_image_info *spl_image)
 {
 	unsigned long machid = 0xffffffff;
@@ -62,4 +72,5 @@ void __noreturn jump_to_image_linux(struct spl_image_info *spl_image)
 	cleanup_before_linux();
 	image_entry(0, machid, spl_image->arg);
 }
+#endif	/* CONFIG_ARM64 */
 #endif

board/freescale/ls1043ardb/ddr.c

@@ -169,17 +169,63 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 
 	return 0;
 }
+#else
+
+phys_size_t fixed_sdram(void)
+{
+	int i;
+	char buf[32];
+	fsl_ddr_cfg_regs_t ddr_cfg_regs;
+	phys_size_t ddr_size;
+	ulong ddr_freq, ddr_freq_mhz;
+
+	ddr_freq = get_ddr_freq(0);
+	ddr_freq_mhz = ddr_freq / 1000000;
+
+	printf("Configuring DDR for %s MT/s data rate\n",
+	       strmhz(buf, ddr_freq));
+
+	for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
+		if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
+		    (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
+			memcpy(&ddr_cfg_regs,
+			       fixed_ddr_parm_0[i].ddr_settings,
+			       sizeof(ddr_cfg_regs));
+			break;
+		}
+	}
+
+	if (fixed_ddr_parm_0[i].max_freq == 0)
+		panic("Unsupported DDR data rate %s MT/s data rate\n",
+		      strmhz(buf, ddr_freq));
+
+	ddr_size = (phys_size_t)2048 * 1024 * 1024;
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+	return ddr_size;
+}
 #endif
 
 int fsl_initdram(void)
 {
 	phys_size_t dram_size;
 
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
 	puts("Initializing DDR....\n");
 	dram_size = fsl_ddr_sdram();
 #else
 	dram_size =  fsl_ddr_sdram_size();
+#endif
+#else
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
+	puts("Initialzing DDR using fixed setting\n");
+	dram_size = fixed_sdram();
+#else
+	gd->ram_size = 0x80000000;
+
+	return 0;
+#endif
 #endif
 	erratum_a008850_post();
 

board/freescale/ls1043ardb/ddr.h

@@ -45,4 +45,73 @@ static const struct board_specific_parameters *udimms[] = {
 	udimm0,
 };
 
+#ifndef CONFIG_SYS_DDR_RAW_TIMING
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1600 = {
+	.cs[0].bnds = 0x0000007F,
+	.cs[1].bnds = 0,
+	.cs[2].bnds = 0,
+	.cs[3].bnds = 0,
+	.cs[0].config = 0x80040322,
+	.cs[0].config_2 = 0,
+	.cs[1].config = 0,
+	.cs[1].config_2 = 0,
+	.cs[2].config = 0,
+	.cs[3].config = 0,
+	.timing_cfg_3 = 0x010C1000,
+	.timing_cfg_0 = 0x91550018,
+	.timing_cfg_1 = 0xBBB48C42,
+	.timing_cfg_2 = 0x0048C111,
+	.ddr_sdram_cfg = 0xC50C0008,
+	.ddr_sdram_cfg_2 = 0x00401100,
+	.ddr_sdram_cfg_3 = 0,
+	.ddr_sdram_mode = 0x03010210,
+	.ddr_sdram_mode_2 = 0,
+	.ddr_sdram_mode_3 = 0x00010210,
+	.ddr_sdram_mode_4 = 0,
+	.ddr_sdram_mode_5 = 0x00010210,
+	.ddr_sdram_mode_6 = 0,
+	.ddr_sdram_mode_7 = 0x00010210,
+	.ddr_sdram_mode_8 = 0,
+	.ddr_sdram_mode_9 = 0x00000500,
+	.ddr_sdram_mode_10 = 0x04000000,
+	.ddr_sdram_mode_11 = 0x00000400,
+	.ddr_sdram_mode_12 = 0x04000000,
+	.ddr_sdram_mode_13 = 0x00000400,
+	.ddr_sdram_mode_14 = 0x04000000,
+	.ddr_sdram_mode_15 = 0x00000400,
+	.ddr_sdram_mode_16 = 0x04000000,
+	.ddr_sdram_interval = 0x18600618,
+	.ddr_data_init = 0xDEADBEEF,
+	.ddr_sdram_clk_cntl = 0x03000000,
+	.ddr_init_addr = 0,
+	.ddr_init_ext_addr = 0,
+	.timing_cfg_4 = 0x00000002,
+	.timing_cfg_5 = 0x03401400,
+	.timing_cfg_6 = 0,
+	.timing_cfg_7 = 0x13300000,
+	.timing_cfg_8 = 0x02115600,
+	.timing_cfg_9 = 0,
+	.ddr_zq_cntl = 0x8A090705,
+	.ddr_wrlvl_cntl = 0x8675F607,
+	.ddr_wrlvl_cntl_2 = 0x07090800,
+	.ddr_wrlvl_cntl_3 = 0,
+	.ddr_sr_cntr = 0,
+	.ddr_sdram_rcw_1 = 0,
+	.ddr_sdram_rcw_2 = 0,
+	.ddr_cdr1 = 0x80040000,
+	.ddr_cdr2 = 0x0000A181,
+	.dq_map_0 = 0,
+	.dq_map_1 = 0,
+	.dq_map_2 = 0,
+	.dq_map_3 = 0,
+	.debug[28] = 0x00700046,
+
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+	{1550, 1650, &ddr_cfg_regs_1600},
+	{0, 0, NULL}
+};
+
+#endif
 #endif

board/freescale/ls1088a/eth_ls1088aqds.c

@@ -14,14 +14,13 @@
 #include <fm_eth.h>
 #include <i2c.h>
 #include <miiphy.h>
+#include <fsl-mc/fsl_mc.h>
 #include <fsl-mc/ldpaa_wriop.h>
 
 #include "../common/qixis.h"
 
 #include "ls1088a_qixis.h"
 
-#define MC_BOOT_ENV_VAR "mcinitcmd"
-
 #ifdef CONFIG_FSL_MC_ENET
 
 #define SFP_TX		0
@@ -612,7 +611,6 @@ static void ls1088a_handle_phy_interface_rgmii(int dpmac_id)
 int board_eth_init(bd_t *bis)
 {
 	int error = 0, i;
-	char *mc_boot_env_var;
 #ifdef CONFIG_FSL_MC_ENET
 	struct memac_mdio_info *memac_mdio0_info;
 	char *env_hwconfig = env_get("hwconfig");
@@ -655,9 +653,6 @@ int board_eth_init(bd_t *bis)
 		}
 	}
 
-	mc_boot_env_var = env_get(MC_BOOT_ENV_VAR);
-	if (mc_boot_env_var)
-		run_command_list(mc_boot_env_var, -1, 0);
 	error = cpu_eth_init(bis);
 
 	if (hwconfig_f("xqsgmii", env_hwconfig)) {
@@ -681,3 +676,10 @@ int board_eth_init(bd_t *bis)
 	error = pci_eth_init(bis);
 	return error;
 }
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+	mc_env_boot();
+}
+#endif /* CONFIG_RESET_PHY_R */

board/freescale/ls1088a/eth_ls1088ardb.c

@@ -15,15 +15,14 @@
 #include <asm/io.h>
 #include <exports.h>
 #include <asm/arch/fsl_serdes.h>
+#include <fsl-mc/fsl_mc.h>
 #include <fsl-mc/ldpaa_wriop.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define MC_BOOT_ENV_VAR "mcinitcmd"
 int board_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_FSL_MC_ENET)
-	char *mc_boot_env_var;
 	int i, interface;
 	struct memac_mdio_info mdio_info;
 	struct mii_dev *dev;
@@ -92,11 +91,15 @@ int board_eth_init(bd_t *bis)
 	dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
 	wriop_set_mdio(WRIOP1_DPMAC2, dev);
 
-	mc_boot_env_var = env_get(MC_BOOT_ENV_VAR);
-	if (mc_boot_env_var)
-		run_command_list(mc_boot_env_var, -1, 0);
 	cpu_eth_init(bis);
 #endif /* CONFIG_FMAN_ENET */
 
 	return pci_eth_init(bis);
 }
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+	mc_env_boot();
+}
+#endif /* CONFIG_RESET_PHY_R */

cmd/spl.c

@@ -121,9 +121,11 @@ static int spl_export(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 				(void *)images.ft_addr);
 			env_set_addr("fdtargsaddr", images.ft_addr);
 			env_set_hex("fdtargslen", fdt_totalsize(images.ft_addr));
+#ifdef CONFIG_CMD_SPL_WRITE_SIZE
 			if (fdt_totalsize(images.ft_addr) >
 			    CONFIG_CMD_SPL_WRITE_SIZE)
 				puts("WARN: FDT size > CMD_SPL_WRITE_SIZE\n");
+#endif
 			break;
 #endif
 		case SPL_EXPORT_ATAGS:

common/spl/spl.c

@@ -258,6 +258,12 @@ static int spl_common_init(bool setup_malloc)
 	return 0;
 }
 
+void spl_set_bd(void)
+{
+	if (!gd->bd)
+		gd->bd = &bdata;
+}
+
 int spl_early_init(void)
 {
 	int ret;
@@ -365,7 +371,9 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 	struct spl_image_info spl_image;
 
 	debug(">>spl:board_init_r()\n");
-	gd->bd = &bdata;
+
+	spl_set_bd();
+
 #ifdef CONFIG_SPL_OS_BOOT
 	dram_init_banksize();
 #endif

configs/ls1021aiot_qspi_defconfig

@@ -3,6 +3,7 @@ CONFIG_TARGET_LS1021AIOT=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
 CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y

configs/ls1021aiot_sdcard_defconfig

@@ -3,6 +3,7 @@ CONFIG_TARGET_LS1021AIOT=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
 CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_CMD_BOOTZ=y
 CONFIG_SPL=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8

configs/ls1043ardb_nand_SECURE_BOOT_defconfig

@@ -17,6 +17,7 @@ CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
 CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
 CONFIG_SPL_CRYPTO_SUPPORT=y

configs/ls1043ardb_nand_defconfig

@@ -16,6 +16,7 @@ CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
 CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
 CONFIG_SPL_ENV_SUPPORT=y

configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig

@@ -18,6 +18,7 @@ CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
 CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
 CONFIG_SPL_CRYPTO_SUPPORT=y

configs/ls1043ardb_sdcard_defconfig

@@ -3,6 +3,7 @@ CONFIG_TARGET_LS1043ARDB=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_FSL_LS_PPA=y
+CONFIG_SPL_FSL_LS_PPA=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
@@ -17,6 +18,7 @@ CONFIG_BOOTDELAY=10
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m@0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
 CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
 CONFIG_SPL_ENV_SUPPORT=y

include/configs/ls1021aiot.h

@@ -276,7 +276,6 @@
 
 #define CONFIG_OF_BOARD_SETUP
 #define CONFIG_OF_STDOUT_VIA_ALIAS
-#define CONFIG_CMD_BOOTZ
 
 #define CONFIG_MISC_INIT_R
 

include/configs/ls1043a_common.h

@@ -73,10 +73,10 @@
 #define CONFIG_SPL_STACK		0x1001e000
 #define CONFIG_SPL_PAD_TO		0x1d000
 
-#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
-					CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
+					CONFIG_SPL_BSS_MAX_SIZE)
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
-#define CONFIG_SPL_BSS_START_ADDR	0x80100000
+#define CONFIG_SPL_BSS_START_ADDR	0x8f000000
 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
 
 #ifdef CONFIG_SECURE_BOOT
@@ -280,6 +280,7 @@
 	"load_addr=0xa0000000\0"		\
 	"kernel_size=0x2800000\0"		\
 	"console=ttyS0,115200\0"		\
+	"boot_os=y\0"				\
 	"mtdparts=" MTDPARTS_DEFAULT "\0"	\
 	BOOTENV					\
 	"boot_scripts=ls1043ardb_boot.scr\0"	\

include/configs/ls1043ardb.h

@@ -28,13 +28,13 @@
 
 #define CONFIG_SYS_SPD_BUS_NUM		0
 
-#define CONFIG_FSL_DDR_BIST
 #ifndef CONFIG_SPL
-#define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
-#endif
 #define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
+#define CONFIG_FSL_DDR_BIST
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
+#endif
 
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
@@ -46,6 +46,11 @@
 
 #ifdef CONFIG_SD_BOOT
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
+#define CONFIG_CMD_SPL
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x90000000
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x10000
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x500
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	30
 #endif
 
 /*

include/configs/ls1046a_common.h

@@ -183,7 +183,7 @@
 #define CONFIG_ENV_SPI_MODE		0x03
 #elif defined(CONFIG_NAND_BOOT)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_FMAN_FW_ADDR		(72 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_FMAN_FW_ADDR		(36 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR		0x60900000

include/configs/ls1046aqds.h

@@ -435,7 +435,7 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_ENV_SIZE			0x2000
-#define CONFIG_ENV_OFFSET		(24 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET		(12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SD_BOOT)
 #define CONFIG_ENV_OFFSET		(3 * 1024 * 1024)
 #define CONFIG_SYS_MMC_ENV_DEV		0

include/configs/ls1088a_common.h

@@ -122,6 +122,12 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH	0x200000
 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET	0x07000000
+
+/* Define phy_reset function to boot the MC based on mcinitcmd.
+ * This happens late enough to properly fixup u-boot env MAC addresses.
+ */
+#define CONFIG_RESET_PHY_R
+
 /*
  * Carve out a DDR region which will not be used by u-boot/Linux
  *

include/spl.h

@@ -68,6 +68,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
 void preloader_console_init(void);
 u32 spl_boot_device(void);
 u32 spl_boot_mode(const u32 boot_device);
+void spl_set_bd(void);
 
 /**
  * spl_set_header_raw_uboot() - Set up a standard SPL image structure