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@@ -26,7 +26,17 @@
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#define TCLR_PRE BIT(5) /* Pre-scaler enable */
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#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
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#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
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-
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+#define TCLR_CE BIT(6) /* compare mode enable */
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+#define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */
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+#define TCLR_TCM BIT(8) /* edge detection of input pin*/
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+#define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */
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+#define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/
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+#define TCLR_CAPTMODE BIT(13) /* capture mode */
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+#define TCLR_GPOCFG BIT(14) /* 0=output,1=input */
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+
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+#define TCFG_RESET BIT(0) /* software reset */
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+#define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */
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+#define TCFG_IDLEMOD_SHIFT (2) /* power management */
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/* device type */
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#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
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#define TST_DEVICE 0x0
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@@ -87,7 +97,8 @@ struct cm_wkuppll {
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unsigned int wkctrlclkctrl; /* offset 0x04 */
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unsigned int wkgpio0clkctrl; /* offset 0x08 */
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unsigned int wkl4wkclkctrl; /* offset 0x0c */
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- unsigned int resv2[4];
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+ unsigned int timer0clkctrl; /* offset 0x10 */
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+ unsigned int resv2[3];
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unsigned int idlestdpllmpu; /* offset 0x20 */
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unsigned int resv3[2];
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unsigned int clkseldpllmpu; /* offset 0x2c */
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@@ -121,7 +132,9 @@ struct cm_wkuppll {
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unsigned int wkup_uart0ctrl; /* offset 0xB4 */
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unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
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unsigned int wkup_adctscctrl; /* offset 0xBC */
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- unsigned int resv12[6];
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+ unsigned int resv12;
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+ unsigned int timer1clkctrl; /* offset 0xC4 */
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+ unsigned int resv13[4];
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unsigned int divm6dpllcore; /* offset 0xD8 */
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};
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@@ -178,7 +191,9 @@ struct cm_perpll {
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unsigned int epwmss2clkctrl; /* offset 0xD8 */
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unsigned int l3instrclkctrl; /* offset 0xDC */
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unsigned int l3clkctrl; /* Offset 0xE0 */
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- unsigned int resv8[4];
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+ unsigned int resv8[2];
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+ unsigned int timer5clkctrl; /* offset 0xEC */
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+ unsigned int timer6clkctrl; /* offset 0xF0 */
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unsigned int mmc1clkctrl; /* offset 0xF4 */
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unsigned int mmc2clkctrl; /* offset 0xF8 */
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unsigned int resv9[8];
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@@ -191,9 +206,17 @@ struct cm_perpll {
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/* Encapsulating Display pll registers */
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struct cm_dpll {
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- unsigned int resv1[2];
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+ unsigned int resv1;
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+ unsigned int clktimer7clk; /* offset 0x04 */
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unsigned int clktimer2clk; /* offset 0x08 */
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- unsigned int resv2[10];
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+ unsigned int clktimer3clk; /* offset 0x0C */
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+ unsigned int clktimer4clk; /* offset 0x10 */
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+ unsigned int resv2;
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+ unsigned int clktimer5clk; /* offset 0x18 */
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+ unsigned int clktimer6clk; /* offset 0x1C */
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+ unsigned int resv3[2];
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+ unsigned int clktimer1clk; /* offset 0x28 */
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+ unsigned int resv4[2];
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unsigned int clklcdcpixelclk; /* offset 0x34 */
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};
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#else
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