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@@ -101,12 +101,50 @@ static inline void final_mmu_setup(void)
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{
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u64 tlb_addr_save = gd->arch.tlb_addr;
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unsigned int el = current_el();
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-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
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int index;
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-#endif
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mem_map = final_map;
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+ /* Update mapping for DDR to actual size */
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+ for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
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+ /*
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+ * Find the entry for DDR mapping and update the address and
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+ * size. Zero-sized mapping will be skipped when creating MMU
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+ * table.
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+ */
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+ switch (final_map[index].virt) {
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+ case CONFIG_SYS_FSL_DRAM_BASE1:
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+ final_map[index].virt = gd->bd->bi_dram[0].start;
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+ final_map[index].phys = gd->bd->bi_dram[0].start;
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+ final_map[index].size = gd->bd->bi_dram[0].size;
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+ break;
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+#ifdef CONFIG_SYS_FSL_DRAM_BASE2
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+ case CONFIG_SYS_FSL_DRAM_BASE2:
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+#if (CONFIG_NR_DRAM_BANKS >= 2)
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+ final_map[index].virt = gd->bd->bi_dram[1].start;
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+ final_map[index].phys = gd->bd->bi_dram[1].start;
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+ final_map[index].size = gd->bd->bi_dram[1].size;
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+#else
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+ final_map[index].size = 0;
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+#endif
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+ break;
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+#endif
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+#ifdef CONFIG_SYS_FSL_DRAM_BASE3
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+ case CONFIG_SYS_FSL_DRAM_BASE3:
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+#if (CONFIG_NR_DRAM_BANKS >= 3)
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+ final_map[index].virt = gd->bd->bi_dram[2].start;
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+ final_map[index].phys = gd->bd->bi_dram[2].start;
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+ final_map[index].size = gd->bd->bi_dram[2].size;
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+#else
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+ final_map[index].size = 0;
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+#endif
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+ break;
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+#endif
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+ default:
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+ break;
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+ }
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+ }
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+
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#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
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if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
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if (el == 3) {
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