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@@ -46,6 +46,7 @@
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/* Wrap bit, last descriptor */
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#define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
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#define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
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+#define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
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#define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
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#define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
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@@ -405,14 +406,19 @@ static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
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u32 addr, size;
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struct zynq_gem_priv *priv = dev->priv;
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struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
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+ struct emac_bd *current_bd = &priv->tx_bd[1];
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/* Setup Tx BD */
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memset(priv->tx_bd, 0, sizeof(struct emac_bd));
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priv->tx_bd->addr = (ulong)ptr;
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priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
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- ZYNQ_GEM_TXBUF_LAST_MASK |
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- ZYNQ_GEM_TXBUF_WRAP_MASK;
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+ ZYNQ_GEM_TXBUF_LAST_MASK;
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+ /* Dummy descriptor to mark it as the last in descriptor chain */
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+ current_bd->addr = 0x0;
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+ current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
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+ ZYNQ_GEM_TXBUF_LAST_MASK|
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+ ZYNQ_GEM_TXBUF_USED_MASK;
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/* setup BD */
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writel((ulong)priv->tx_bd, ®s->txqbase);
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