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@@ -66,7 +66,7 @@ DECLARE_GLOBAL_DATA_PTR;
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#define IOX_SDI IMX_GPIO_NR(5, 10)
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#define IOX_STCP IMX_GPIO_NR(5, 7)
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#define IOX_SHCP IMX_GPIO_NR(5, 11)
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-#define IOX_OE IMX_GPIO_NR(5, 18)
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+#define IOX_OE IMX_GPIO_NR(5, 8)
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static iomux_v3_cfg_t const iox_pads[] = {
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/* IOX_SDI */
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@@ -117,7 +117,7 @@ static enum qn_level seq[3][2] = {
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static enum qn_func qn_output[8] = {
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qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset,
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- qn_disable, qn_enable
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+ qn_disable, qn_disable
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};
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static void iox74lv_init(void)
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@@ -154,8 +154,6 @@ static void iox74lv_init(void)
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* shift register will be output to pins
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*/
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gpio_direction_output(IOX_STCP, 1);
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-
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- gpio_direction_output(IOX_OE, 1);
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};
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#ifdef CONFIG_SYS_I2C_MXC
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@@ -305,7 +303,7 @@ static void setup_iomux_uart(void)
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#define QSPI_PAD_CTRL1 \
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(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
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- PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm)
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+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
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static iomux_v3_cfg_t const quadspi_pads[] = {
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MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
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