ARM: dts: uniphier: add device nodes for System Control blocks

These are mainly used for controlling clocks and resets.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

arch/arm/dts/uniphier-common32.dtsi

@@ -101,6 +101,14 @@
 			reg = <0x5f801000 0xe00>;
 		};
 
+		sysctrl: sysctrl@61840000 {
+			/* specify compatible in each SoC DTSI */
+			reg = <0x61840000 0x4000>;
+			#clock-cells = <1>;
+			clock-names = "ref";
+			clocks = <&refclk>;
+		};
+
 		nand: nand@68000000 {
 			compatible = "denali,denali-nand-dt";
 			reg = <0x68000000 0x20>, <0x68100000 0x1000>;

arch/arm/dts/uniphier-ph1-ld4.dtsi

@@ -160,3 +160,7 @@
 &pinctrl {
 	compatible = "socionext,ph1-ld4-pinctrl", "syscon";
 };
+
+&sysctrl {
+	compatible = "socionext,ph1-ld4-sysctrl";
+};

arch/arm/dts/uniphier-ph1-pro4.dtsi

@@ -200,3 +200,7 @@
 &pinctrl {
 	compatible = "socionext,ph1-pro4-pinctrl", "syscon";
 };
+
+&sysctrl {
+	compatible = "socionext,ph1-pro4-sysctrl";
+};

arch/arm/dts/uniphier-ph1-pro5.dtsi

@@ -194,3 +194,7 @@
 &pinctrl {
 	compatible = "socionext,ph1-pro5-pinctrl", "syscon";
 };
+
+&sysctrl {
+	compatible = "socionext,ph1-pro5-sysctrl";
+};

arch/arm/dts/uniphier-ph1-sld3.dtsi

@@ -206,6 +206,14 @@
 			interrupts = <0 83 4>;
 		};
 
+		sysctrl: sysctrl@f1840000 {
+			compatible = "socionext,ph1-sld3-sysctrl";
+			reg = <0xf1840000 0x4000>;
+			#clock-cells = <1>;
+			clock-names = "ref";
+			clocks = <&refclk>;
+		};
+
 		nand: nand@f8000000 {
 			compatible = "denali,denali-nand-dt";
 			reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;

arch/arm/dts/uniphier-ph1-sld8.dtsi

@@ -160,3 +160,7 @@
 &pinctrl {
 	compatible = "socionext,ph1-sld8-pinctrl", "syscon";
 };
+
+&sysctrl {
+	compatible = "socionext,ph1-sld8-sysctrl";
+};

arch/arm/dts/uniphier-proxstream2.dtsi

@@ -205,3 +205,7 @@
 &pinctrl {
 	compatible = "socionext,proxstream2-pinctrl", "syscon";
 };
+
+&sysctrl {
+	compatible = "socionext,proxstream2-sysctrl";
+};