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@@ -45,154 +45,154 @@
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*/
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const iop_conf_t iop_conf_tab[4][32] = {
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- /* Port A */
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- { /* conf ppar psor pdir podr pdat */
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- /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* PA31 */
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- /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* PA30 */
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- /* PA29 */ { 0, 0, 0, 0, 0, 0 }, /* PA29 */
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- /* PA28 */ { 0, 0, 0, 0, 0, 0 }, /* PA28 */
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- /* PA27 */ { 0, 0, 0, 0, 0, 0 }, /* PA27 */
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- /* PA26 */ { 0, 0, 0, 0, 0, 0 }, /* PA26 */
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- /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
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- /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
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- /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
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- /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
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- /* PA21 */ { 0, 0, 0, 0, 0, 0 }, /* PA21 */
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- /* PA20 */ { 0, 0, 0, 0, 0, 0 }, /* PA20 */
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- /* PA19 */ { 0, 0, 0, 0, 0, 0 }, /* PA19 */
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- /* PA18 */ { 0, 0, 0, 0, 0, 0 }, /* PA18 */
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- /* PA17 */ { 0, 0, 0, 0, 0, 0 }, /* PA17 */
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- /* PA16 */ { 0, 0, 0, 0, 0, 0 }, /* PA16 */
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- /* PA15 */ { 0, 0, 0, 0, 0, 0 }, /* PA15 */
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- /* PA14 */ { 0, 0, 0, 0, 0, 0 }, /* PA14 */
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- /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
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- /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
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- /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
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- /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
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- /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TxD */
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- /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RxD */
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- /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
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- /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
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- /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
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- /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
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- /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
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- /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
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- /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
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- /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
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- },
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-
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- /* Port B */
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- { /* conf ppar psor pdir podr pdat */
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- /* PB31 */ { 0, 0, 0, 0, 0, 0 }, /* PB31 */
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- /* PB30 */ { 0, 0, 0, 0, 0, 0 }, /* PB30 */
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- /* PB29 */ { 0, 0, 0, 0, 0, 0 }, /* PB29 */
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- /* PB28 */ { 0, 0, 0, 0, 0, 0 }, /* PB28 */
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- /* PB27 */ { 0, 0, 0, 0, 0, 0 }, /* PB27 */
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- /* PB26 */ { 0, 0, 0, 0, 0, 0 }, /* PB26 */
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- /* PB25 */ { 0, 0, 0, 0, 0, 0 }, /* PB25 */
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- /* PB24 */ { 0, 0, 0, 0, 0, 0 }, /* PB24 */
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- /* PB23 */ { 0, 0, 0, 0, 0, 0 }, /* PB23 */
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- /* PB22 */ { 0, 0, 0, 0, 0, 0 }, /* PB22 */
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- /* PB21 */ { 0, 0, 0, 0, 0, 0 }, /* PB21 */
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- /* PB20 */ { 0, 0, 0, 0, 0, 0 }, /* PB20 */
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- /* PB19 */ { 0, 0, 0, 0, 0, 0 }, /* PB19 */
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- /* PB18 */ { 0, 0, 0, 0, 0, 0 }, /* PB18 */
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- /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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- /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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- /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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- /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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- /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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- /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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- /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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- /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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- /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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- /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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- /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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- /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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- /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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- /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
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- },
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-
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- /* Port C */
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- { /* conf ppar psor pdir podr pdat */
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- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
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- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
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- /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
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- /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
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- /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
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- /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
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- /* PC25 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RxClk */
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- /* PC24 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 TxClk */
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- /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
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- /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
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- /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
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- /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
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- /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
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- /* PC18 */ { 0, 0, 0, 0, 0, 0 }, /* PC18 */
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- /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
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- /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
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- /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
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- /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
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- /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
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- /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
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- /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
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- /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
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- /* PC9 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CTS */
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- /* PC8 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CD */
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- /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
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- /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
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- /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
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- /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
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- /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
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- /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
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- /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
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- /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
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- },
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-
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- /* Port D */
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- { /* conf ppar psor pdir podr pdat */
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- /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */
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- /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
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- /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
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- /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
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- /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
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- /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
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- /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
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- /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
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- /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
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- /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: RXD */
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- /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: TXD */
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- /* PD20 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: RTS */
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- /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
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- /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
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- /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
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- /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
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+ /* Port A */
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+ { /* conf ppar psor pdir podr pdat */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA31 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA30 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA29 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA28 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA27 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA26 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA21 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA20 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA19 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA18 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA17 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA16 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA15 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA14 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
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+ { 1, 1, 0, 1, 0, 0 }, /* PA9 SMC2 TxD */
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+ { 1, 1, 0, 0, 0, 0 }, /* PA8 SMC2 RxD */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
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+ { 0, 0, 0, 0, 0, 0 } /* PA0 */
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+ },
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+
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+ /* Port B */
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+ { /* conf ppar psor pdir podr pdat */
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+ { 0, 0, 0, 0, 0, 0 }, /* PB31 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PB30 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PB29 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PB28 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PB27 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PB26 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PB25 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PB24 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PB23 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PB22 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PB21 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PB20 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PB19 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PB18 */
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+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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+ { 0, 0, 0, 0, 0, 0 } /* non-existent */
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+ },
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+
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+ /* Port C */
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+ { /* conf ppar psor pdir podr pdat */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
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+ { 1, 1, 0, 0, 0, 0 }, /* PC25 RxClk */
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+ { 1, 1, 0, 0, 0, 0 }, /* PC24 TxClk */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC18 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
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+ { 1, 1, 0, 0, 0, 0 }, /* PC9 SCC4: CTS */
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+ { 1, 1, 0, 0, 0, 0 }, /* PC8 SCC4: CD */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
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+ },
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+
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+ /* Port D */
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+ { /* conf ppar psor pdir podr pdat */
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+ { 0, 0, 0, 0, 0, 0 }, /* PD31 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
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+ { 1, 1, 0, 0, 0, 0 }, /* PD22 SCC4: RXD */
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+ { 1, 1, 0, 1, 0, 0 }, /* PD21 SCC4: TXD */
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+ { 1, 1, 0, 1, 0, 0 }, /* PD20 SCC4: RTS */
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+ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
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+ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
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#if defined(CONFIG_HARD_I2C)
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- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
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- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
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+ { 1, 1, 1, 0, 1, 0 }, /* PD15 I2C SDA */
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+ { 1, 1, 1, 0, 1, 0 }, /* PD14 I2C SCL */
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#else
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- /* PD15 */ { 1, 0, 0, 0, 1, 1 }, /* PD15 */
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- /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* PD14 */
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+ { 1, 0, 0, 0, 1, 1 }, /* PD15 */
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+ { 1, 0, 0, 1, 1, 1 }, /* PD14 */
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#endif
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- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
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- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
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- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
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- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
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- /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
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- /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
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- /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
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- /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
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- /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
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|
|
- /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
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|
|
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
|
|
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
|
|
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
|
|
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
|
|
|
- }
|
|
|
+ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
|
|
|
+ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
|
|
|
+ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
|
|
|
+ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
|
|
|
+ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
|
|
|
+ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
|
|
|
+ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
|
|
|
+ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
|
|
|
+ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
|
|
|
+ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
|
|
|
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
|
|
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
|
|
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
|
|
|
+ { 0, 0, 0, 0, 0, 0 } /* non-existent */
|
|
|
+ }
|
|
|
};
|
|
|
|
|
|
/*
|
|
@@ -237,7 +237,8 @@ static long int try_init(memctl8260_t *memctl, ulong sdmr,
|
|
|
* accessing the SDRAM with a single-byte transaction."
|
|
|
*
|
|
|
* The appropriate BRx/ORx registers have already been set when we
|
|
|
- * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
|
|
|
+ * get here. The SDRAM can be accessed at the address
|
|
|
+ * CONFIG_SYS_SDRAM_BASE.
|
|
|
*/
|
|
|
|
|
|
out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_PREA);
|
|
@@ -257,7 +258,7 @@ static long int try_init(memctl8260_t *memctl, ulong sdmr,
|
|
|
size = get_ram_size((long *)base, maxsize);
|
|
|
out_be32(&memctl->memc_or1, orx | ~(size - 1));
|
|
|
|
|
|
- return (size);
|
|
|
+ return size;
|
|
|
}
|
|
|
|
|
|
phys_size_t initdram(int board_type)
|
|
@@ -279,7 +280,7 @@ phys_size_t initdram(int board_type)
|
|
|
|
|
|
icache_enable();
|
|
|
|
|
|
- return (psize);
|
|
|
+ return psize;
|
|
|
}
|
|
|
|
|
|
int checkboard(void)
|