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@@ -28,7 +28,17 @@
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/* SOC specific definations */
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#define INTREG_BASE 0xd0000000
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#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
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+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYS_MVEBU_DDR_A38X)
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+/*
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+ * On A38x switching the regs base address without running from
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+ * SDRAM doesn't seem to work. So let the SPL still use the
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+ * default base address and switch to the new address in the
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+ * main u-boot later.
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+ */
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+#define SOC_REGS_PHY_BASE 0xd0000000
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+#else
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#define SOC_REGS_PHY_BASE 0xf1000000
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+#endif
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#define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)
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#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
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