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@@ -255,6 +255,23 @@ static void clear_mmdc_ch_mask(void)
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writel(0, &mxc_ccm->ccdr);
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}
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+static void init_bandgap(void)
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+{
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+ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
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+ /*
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+ * Ensure the bandgap has stabilized.
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+ */
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+ while (!(readl(&anatop->ana_misc0) & 0x80))
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+ ;
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+ /*
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+ * For best noise performance of the analog blocks using the
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+ * outputs of the bandgap, the reftop_selfbiasoff bit should
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+ * be set.
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+ */
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+ writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
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+}
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+
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+
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#ifdef CONFIG_MX6SL
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static void set_preclk_from_osc(void)
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{
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@@ -274,6 +291,13 @@ int arch_cpu_init(void)
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/* Need to clear MMDC_CHx_MASK to make warm reset work. */
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clear_mmdc_ch_mask();
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+ /*
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+ * Disable self-bias circuit in the analog bandap.
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+ * The self-bias circuit is used by the bandgap during startup.
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+ * This bit should be set after the bandgap has initialized.
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+ */
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+ init_bandgap();
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+
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/*
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* When low freq boot is enabled, ROM will not set AHB
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* freq, so we need to ensure AHB freq is 132MHz in such
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