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@@ -321,7 +321,7 @@ static unsigned int exynos_dp_link_start(struct exynos_dp *regs,
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static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *regs)
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{
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- unsigned int ret = EXYNOS_DP_SUCCESS;
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+ unsigned int ret;
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exynos_dp_set_training_pattern(regs, DP_NONE);
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@@ -339,7 +339,7 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode(
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struct exynos_dp *regs, unsigned char enable)
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{
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unsigned char data;
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- unsigned int ret = EXYNOS_DP_SUCCESS;
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+ unsigned int ret;
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ret = exynos_dp_read_byte_from_dpcd(regs, DPCD_LANE_COUNT_SET,
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&data);
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@@ -366,7 +366,7 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode(
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static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *regs,
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unsigned char enhance_mode)
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{
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- unsigned int ret = EXYNOS_DP_SUCCESS;
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+ unsigned int ret;
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ret = exynos_dp_enable_rx_to_enhanced_mode(regs, enhance_mode);
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if (ret != EXYNOS_DP_SUCCESS) {
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@@ -416,7 +416,7 @@ static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *regs,
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static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *regs,
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unsigned char lane_num, unsigned char *sw, unsigned char *em)
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{
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- unsigned int ret = EXYNOS_DP_SUCCESS;
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+ unsigned int ret;
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unsigned char buf;
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unsigned int dpcd_addr;
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unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4};
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@@ -484,7 +484,7 @@ static int exynos_dp_reduce_link_rate(struct exynos_dp *regs,
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static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *regs,
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struct exynos_dp_priv *priv)
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{
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- unsigned int ret = EXYNOS_DP_SUCCESS;
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+ unsigned int ret;
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unsigned char lane_stat;
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unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, };
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unsigned int i;
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@@ -594,7 +594,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *regs,
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static unsigned int exynos_dp_process_equalizer_training(
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struct exynos_dp *regs, struct exynos_dp_priv *priv)
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{
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- unsigned int ret = EXYNOS_DP_SUCCESS;
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+ unsigned int ret;
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unsigned char lane_stat, adj_req_sw, adj_req_em, i;
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unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,};
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unsigned char interlane_aligned = 0;
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