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@@ -4978,8 +4978,8 @@ e1000_configure_tx(struct e1000_hw *hw)
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unsigned long tipg, tarc;
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uint32_t ipgr1, ipgr2;
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- E1000_WRITE_REG(hw, TDBAL, (unsigned long)tx_base & 0xffffffff);
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- E1000_WRITE_REG(hw, TDBAH, (unsigned long)tx_base >> 32);
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+ E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base));
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+ E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base));
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E1000_WRITE_REG(hw, TDLEN, 128);
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@@ -5103,6 +5103,7 @@ e1000_configure_rx(struct e1000_hw *hw)
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{
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unsigned long rctl, ctrl_ext;
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rx_tail = 0;
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+
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/* make sure receives are disabled while setting up the descriptors */
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rctl = E1000_READ_REG(hw, RCTL);
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E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
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@@ -5122,8 +5123,8 @@ e1000_configure_rx(struct e1000_hw *hw)
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E1000_WRITE_FLUSH(hw);
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}
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/* Setup the Base and Length of the Rx Descriptor Ring */
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- E1000_WRITE_REG(hw, RDBAL, (unsigned long)rx_base & 0xffffffff);
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- E1000_WRITE_REG(hw, RDBAH, (unsigned long)rx_base >> 32);
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+ E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base));
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+ E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base));
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E1000_WRITE_REG(hw, RDLEN, 128);
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