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@@ -280,63 +280,12 @@ success:
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return delta / 1000;
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}
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-#ifndef CONFIG_TIMER
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-void timer_set_base(u64 base)
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-{
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- gd->arch.tsc_base = base;
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-}
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-
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-/*
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- * Get the number of CPU time counter ticks since it was read first time after
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- * restart. This yields a free running counter guaranteed to take almost 6
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- * years to wrap around even at 100GHz clock rate.
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- */
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-u64 notrace get_ticks(void)
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-{
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- u64 now_tick = rdtsc();
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-
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- /* We assume that 0 means the base hasn't been set yet */
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- if (!gd->arch.tsc_base)
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- panic("No tick base available");
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- return now_tick - gd->arch.tsc_base;
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-}
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-#endif /* CONFIG_TIMER */
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-
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/* Get the speed of the TSC timer in MHz */
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unsigned notrace long get_tbclk_mhz(void)
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{
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-#ifdef CONFIG_TIMER
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return get_tbclk() / 1000000;
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-#else
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- unsigned long fast_calibrate;
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-
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- if (gd->arch.tsc_mhz)
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- return gd->arch.tsc_mhz;
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-
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-#ifdef CONFIG_TSC_CALIBRATION_BYPASS
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- fast_calibrate = CONFIG_TSC_FREQ_IN_MHZ;
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-#else
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- fast_calibrate = try_msr_calibrate_tsc();
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- if (!fast_calibrate) {
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-
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- fast_calibrate = quick_pit_calibrate();
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- if (!fast_calibrate)
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- panic("TSC frequency is ZERO");
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- }
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-#endif
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-
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- gd->arch.tsc_mhz = fast_calibrate;
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- return fast_calibrate;
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-#endif
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}
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-#ifndef CONFIG_TIMER
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-unsigned long get_tbclk(void)
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-{
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- return get_tbclk_mhz() * 1000 * 1000;
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-}
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-#endif
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-
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static ulong get_ms_timer(void)
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{
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return (get_ticks() * 1000) / get_tbclk();
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@@ -386,7 +335,6 @@ int timer_init(void)
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return 0;
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}
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-#ifdef CONFIG_TIMER
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static int tsc_timer_get_count(struct udevice *dev, u64 *count)
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{
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u64 now_tick = rdtsc();
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@@ -439,4 +387,3 @@ U_BOOT_DRIVER(tsc_timer) = {
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.ops = &tsc_timer_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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-#endif /* CONFIG_TIMER */
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