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@@ -32,9 +32,13 @@
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#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
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#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
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-
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+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
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+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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+#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
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+#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */
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+#endif
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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@@ -101,13 +105,14 @@
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/*
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* FPGA Driver
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*/
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+#ifdef CONFIG_TARGET_SOCFPGA_GEN5
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#ifdef CONFIG_CMD_FPGA
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#define CONFIG_FPGA
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#define CONFIG_FPGA_ALTERA
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#define CONFIG_FPGA_SOCFPGA
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#define CONFIG_FPGA_COUNT 1
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#endif
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-
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+#endif
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/*
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* L4 OSC1 Timer 0
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*/
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@@ -207,11 +212,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE -4
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-#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
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#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
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#define CONFIG_SYS_NS16550_CLK 1000000
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-#else
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+#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
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+#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
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#define CONFIG_SYS_NS16550_CLK 100000000
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+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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+#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS
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+#define CONFIG_SYS_NS16550_CLK 50000000
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#endif
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#define CONFIG_CONS_INDEX 1
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@@ -298,7 +306,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
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*/
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
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-#define CONFIG_SPL_MAX_SIZE (64 * 1024)
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+#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
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+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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+#define CONFIG_SPL_BOARD_INIT
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+#endif
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/* SPL SDMMC boot support */
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#ifdef CONFIG_SPL_MMC_SUPPORT
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