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@@ -67,13 +67,22 @@ struct sunxi_ccm_reg {
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u32 dram_pll_cfg; /* 0xf8 PLL_DDR cfg register, A33 only */
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u32 mbus_reset; /* 0xfc MBUS reset control, A33 only */
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u32 dram_clk_gate; /* 0x100 DRAM module gating */
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+#ifdef CONFIG_SUNXI_DE2
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+ u32 de_clk_cfg; /* 0x104 DE module clock */
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+#else
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u32 be0_clk_cfg; /* 0x104 BE0 module clock */
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+#endif
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u32 be1_clk_cfg; /* 0x108 BE1 module clock */
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u32 fe0_clk_cfg; /* 0x10c FE0 module clock */
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u32 fe1_clk_cfg; /* 0x110 FE1 module clock */
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u32 mp_clk_cfg; /* 0x114 MP module clock */
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+#ifdef CONFIG_SUNXI_DE2
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+ u32 lcd0_clk_cfg; /* 0x118 LCD0 module clock */
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+ u32 lcd1_clk_cfg; /* 0x11c LCD1 module clock */
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+#else
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u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */
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u32 lcd1_ch0_clk_cfg; /* 0x11c LCD1 CH0 module clock */
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+#endif
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u32 reserved14[3];
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u32 lcd0_ch1_clk_cfg; /* 0x12c LCD0 CH1 module clock */
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u32 lcd1_ch1_clk_cfg; /* 0x130 LCD1 CH1 module clock */
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@@ -85,7 +94,11 @@ struct sunxi_ccm_reg {
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u32 dmic_clk_cfg; /* 0x148 Digital Mic module clock*/
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u32 reserved15;
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u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */
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+#ifdef CONFIG_SUNXI_DE2
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+ u32 hdmi_slow_clk_cfg; /* 0x154 HDMI slow module clock */
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+#else
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u32 ps_clk_cfg; /* 0x154 PS module clock */
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+#endif
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u32 mtc_clk_cfg; /* 0x158 MTC module clock */
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u32 mbus0_clk_cfg; /* 0x15c MBUS0 module clock */
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u32 mbus1_clk_cfg; /* 0x160 MBUS1 module clock */
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@@ -193,6 +206,7 @@ struct sunxi_ccm_reg {
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#define CCM_PLL3_CTRL_N_MASK (0x7f << CCM_PLL3_CTRL_N_SHIFT)
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#define CCM_PLL3_CTRL_N(n) ((((n) - 1) & 0x7f) << 8)
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#define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 24)
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+#define CCM_PLL3_CTRL_LOCK (0x1 << 28)
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#define CCM_PLL3_CTRL_EN (0x1 << 31)
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#define CCM_PLL5_CTRL_M(n) ((((n) - 1) & 0x3) << 0)
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@@ -222,6 +236,16 @@ struct sunxi_ccm_reg {
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#define CCM_MIPI_PLL_CTRL_LDO_EN (0x3 << 22)
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#define CCM_MIPI_PLL_CTRL_EN (0x1 << 31)
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+#define CCM_PLL10_CTRL_M_SHIFT 0
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+#define CCM_PLL10_CTRL_M_MASK (0xf << CCM_PLL10_CTRL_M_SHIFT)
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+#define CCM_PLL10_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
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+#define CCM_PLL10_CTRL_N_SHIFT 8
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+#define CCM_PLL10_CTRL_N_MASK (0x7f << CCM_PLL10_CTRL_N_SHIFT)
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+#define CCM_PLL10_CTRL_N(n) ((((n) - 1) & 0x7f) << 8)
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+#define CCM_PLL10_CTRL_INTEGER_MODE (0x1 << 24)
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+#define CCM_PLL10_CTRL_LOCK (0x1 << 28)
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+#define CCM_PLL10_CTRL_EN (0x1 << 31)
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+
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#define CCM_PLL11_CTRL_N(n) ((((n) - 1) & 0x3f) << 8)
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#define CCM_PLL11_CTRL_SIGMA_DELTA_EN (0x1 << 24)
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#define CCM_PLL11_CTRL_UPD (0x1 << 30)
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@@ -273,9 +297,15 @@ struct sunxi_ccm_reg {
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#define AHB_GATE_OFFSET_DRC0 25
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#define AHB_GATE_OFFSET_DE_FE0 14
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#define AHB_GATE_OFFSET_DE_BE0 12
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+#define AHB_GATE_OFFSET_DE 12
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#define AHB_GATE_OFFSET_HDMI 11
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+#ifndef CONFIG_SUNXI_DE2
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#define AHB_GATE_OFFSET_LCD1 5
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#define AHB_GATE_OFFSET_LCD0 4
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+#else
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+#define AHB_GATE_OFFSET_LCD1 4
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+#define AHB_GATE_OFFSET_LCD0 3
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+#endif
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#define CCM_MMC_CTRL_M(x) ((x) - 1)
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#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8)
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@@ -357,6 +387,12 @@ struct sunxi_ccm_reg {
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#define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24)
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#define CCM_LCD_CH1_CTRL_GATE (0x1 << 31)
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+#define CCM_LCD0_CTRL_GATE (0x1 << 31)
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+#define CCM_LCD0_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
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+
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+#define CCM_LCD1_CTRL_GATE (0x1 << 31)
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+#define CCM_LCD1_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
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+
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#define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
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#define CCM_HDMI_CTRL_PLL_MASK (3 << 24)
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#define CCM_HDMI_CTRL_PLL3 (0 << 24)
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@@ -366,6 +402,8 @@ struct sunxi_ccm_reg {
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#define CCM_HDMI_CTRL_DDC_GATE (0x1 << 30)
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#define CCM_HDMI_CTRL_GATE (0x1 << 31)
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+#define CCM_HDMI_SLOW_CTRL_DDC_GATE (1 << 31)
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+
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#if defined(CONFIG_MACH_SUN50I)
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#define MBUS_CLK_DEFAULT 0x81000002 /* PLL6x2 / 3 */
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#elif defined(CONFIG_MACH_SUN8I)
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@@ -393,9 +431,16 @@ struct sunxi_ccm_reg {
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#define AHB_RESET_OFFSET_DRC0 25
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#define AHB_RESET_OFFSET_DE_FE0 14
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#define AHB_RESET_OFFSET_DE_BE0 12
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+#define AHB_RESET_OFFSET_DE 12
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#define AHB_RESET_OFFSET_HDMI 11
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+#define AHB_RESET_OFFSET_HDMI2 10
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+#ifndef CONFIG_SUNXI_DE2
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#define AHB_RESET_OFFSET_LCD1 5
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#define AHB_RESET_OFFSET_LCD0 4
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+#else
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+#define AHB_RESET_OFFSET_LCD1 4
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+#define AHB_RESET_OFFSET_LCD0 3
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+#endif
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/* ahb_reset2 offsets */
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#define AHB_RESET_OFFSET_EPHY 2
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@@ -418,6 +463,13 @@ struct sunxi_ccm_reg {
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#define CCM_DE_CTRL_PLL10 (5 << 24)
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#define CCM_DE_CTRL_GATE (1 << 31)
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+/* CCM bits common to all Display Engine 2.0 clock ctrl regs */
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+#define CCM_DE2_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
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+#define CCM_DE2_CTRL_PLL_MASK (3 << 24)
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+#define CCM_DE2_CTRL_PLL6_2X (0 << 24)
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+#define CCM_DE2_CTRL_PLL10 (1 << 24)
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+#define CCM_DE2_CTRL_GATE (0x1 << 31)
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+
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/* CCU security switch, H3 only */
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#define CCM_SEC_SWITCH_MBUS_NONSEC (1 << 2)
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#define CCM_SEC_SWITCH_BUS_NONSEC (1 << 1)
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@@ -426,7 +478,9 @@ struct sunxi_ccm_reg {
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#ifndef __ASSEMBLY__
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void clock_set_pll1(unsigned int hz);
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void clock_set_pll3(unsigned int hz);
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+void clock_set_pll3_factors(int m, int n);
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void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
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+void clock_set_pll10(unsigned int hz);
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void clock_set_pll11(unsigned int clk, bool sigma_delta_enable);
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void clock_set_mipi_pll(unsigned int hz);
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unsigned int clock_get_pll3(void);
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