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@@ -214,7 +214,7 @@ static int comphy_pcie_power_up(u32 speed, u32 invert)
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rb_txdclk_pclk_en, /* value */
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rb_txdclk_pclk_en, /* mask */
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POLL_16B_REG); /* 16bit */
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- if (ret == 0)
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+ if (!ret)
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printf("Failed to lock PCIe PLL\n");
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debug_exit();
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@@ -283,7 +283,7 @@ static int comphy_sata_power_up(void)
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bs_pll_ready_tx, /* value */
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bs_pll_ready_tx, /* mask */
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POLL_32B_REG); /* 32bit */
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- if (ret == 0)
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+ if (!ret)
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printf("Failed to lock SATA PLL\n");
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debug_exit();
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@@ -412,7 +412,7 @@ static int comphy_usb3_power_up(u32 type, u32 speed, u32 invert)
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rb_txdclk_pclk_en, /* value */
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rb_txdclk_pclk_en, /* mask */
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POLL_16B_REG); /* 16bit */
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- if (ret == 0)
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+ if (!ret)
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printf("Failed to lock USB3 PLL\n");
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/*
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@@ -492,7 +492,7 @@ static int comphy_usb2_power_up(u8 usb32)
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rb_usb2phy_pllcal_done, /* value */
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rb_usb2phy_pllcal_done, /* mask */
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POLL_32B_REG); /* 32bit */
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- if (ret == 0)
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+ if (!ret)
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printf("Failed to end USB2 PLL calibration\n");
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/* Assert impedance calibration done */
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@@ -500,7 +500,7 @@ static int comphy_usb2_power_up(u8 usb32)
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rb_usb2phy_impcal_done, /* value */
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rb_usb2phy_impcal_done, /* mask */
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POLL_32B_REG); /* 32bit */
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- if (ret == 0)
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+ if (!ret)
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printf("Failed to end USB2 impedance calibration\n");
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/* Assert squetch calibration done */
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@@ -508,7 +508,7 @@ static int comphy_usb2_power_up(u8 usb32)
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rb_usb2phy_sqcal_done, /* value */
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rb_usb2phy_sqcal_done, /* mask */
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POLL_32B_REG); /* 32bit */
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- if (ret == 0)
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+ if (!ret)
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printf("Failed to end USB2 unknown calibration\n");
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/* Assert PLL is ready */
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@@ -517,7 +517,7 @@ static int comphy_usb2_power_up(u8 usb32)
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rb_usb2phy_pll_ready, /* mask */
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POLL_32B_REG); /* 32bit */
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- if (ret == 0)
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+ if (!ret)
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printf("Failed to lock USB2 PLL\n");
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debug_exit();
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@@ -765,7 +765,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
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rb_pll_ready_tx | rb_pll_ready_rx, /* value */
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rb_pll_ready_tx | rb_pll_ready_rx, /* mask */
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POLL_32B_REG); /* 32bit */
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- if (ret == 0)
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+ if (!ret)
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printf("Failed to lock PLL for SGMII PHY %d\n", lane);
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/*
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@@ -787,7 +787,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
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rb_rx_init_done, /* value */
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rb_rx_init_done, /* mask */
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POLL_32B_REG); /* 32bit */
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- if (ret == 0)
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+ if (!ret)
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printf("Failed to init RX of SGMII PHY %d\n", lane);
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debug_exit();
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@@ -818,7 +818,7 @@ void comphy_dedicated_phys_init(void)
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if (node > 0) {
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if (fdtdec_get_is_enabled(blob, node)) {
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ret = comphy_usb2_power_up(usb32);
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- if (ret == 0)
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+ if (!ret)
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printf("Failed to initialize UTMI PHY\n");
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else
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debug("UTMI PHY init succeed\n");
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@@ -836,7 +836,7 @@ void comphy_dedicated_phys_init(void)
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if (node > 0) {
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if (fdtdec_get_is_enabled(blob, node)) {
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ret = comphy_sata_power_up();
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- if (ret == 0)
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+ if (!ret)
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printf("Failed to initialize SATA PHY\n");
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else
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debug("SATA PHY init succeed\n");
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@@ -857,7 +857,7 @@ void comphy_dedicated_phys_init(void)
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if (node > 0) {
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if (fdtdec_get_is_enabled(blob, node)) {
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ret = comphy_emmc_power_up();
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- if (ret == 0)
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+ if (!ret)
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printf("Failed to initialize SDIO/eMMC PHY\n");
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else
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debug("SDIO/eMMC PHY init succeed\n");
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@@ -915,7 +915,7 @@ int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg,
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ret = 1;
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break;
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}
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- if (ret == 0)
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+ if (!ret)
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printf("PLL is not locked - Failed to initialize lane %d\n",
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lane);
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}
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