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@@ -1,6 +1,6 @@
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/*
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- * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
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- * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
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+ * Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at>
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+ * B&R Industrial Automation GmbH - http://www.br-automation.com
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*
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* minimal framebuffer driver for TI's AM335x SoC to be compatible with
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* Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c)
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@@ -12,7 +12,11 @@
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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+#include <asm/io.h>
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#include <asm/arch/hardware.h>
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+#include <asm/arch/omap.h>
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+#include <asm/arch/clock.h>
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+#include <asm/arch/sys_proto.h>
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#include <lcd.h>
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#include "am335x-fb.h"
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@@ -20,6 +24,7 @@
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#error "hw-base address of LCD-Controller (LCD_CNTL_BASE) not defined!"
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#endif
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+#define LCDC_FMAX 200000000
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/* LCD Control Register */
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#define LCD_CLK_DIVISOR(x) ((x) << 8)
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@@ -96,6 +101,7 @@ struct am335x_lcdhw {
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};
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static struct am335x_lcdhw *lcdhw = (void *)LCD_CNTL_BASE;
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+
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DECLARE_GLOBAL_DATA_PTR;
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int lcd_get_size(int *line_length)
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@@ -108,11 +114,16 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
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{
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u32 raster_ctrl = 0;
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- if (0 == gd->fb_base) {
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+ struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
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+ struct dpll_params dpll_disp = { 1, 0, 1, -1, -1, -1, -1 };
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+ unsigned int m, n, d, best_d = 2;
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+ int err = 0, err_r = 0;
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+
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+ if (gd->fb_base == 0) {
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printf("ERROR: no valid fb_base stored in GLOBAL_DATA_PTR!\n");
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return -1;
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}
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- if (0 == panel) {
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+ if (panel == NULL) {
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printf("ERROR: missing ptr to am335x_lcdpanel!\n");
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return -1;
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}
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@@ -132,14 +143,51 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
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return -1;
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}
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+ /* check given clock-frequency */
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+ if (panel->pxl_clk > (LCDC_FMAX / 2)) {
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+ pr_err("am335x-fb: requested pxl-clk: %d not supported!\n",
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+ panel->pxl_clk);
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+ return -1;
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+ }
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+
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debug("setting up LCD-Controller for %dx%dx%d (hfp=%d,hbp=%d,hsw=%d / ",
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panel->hactive, panel->vactive, panel->bpp,
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panel->hfp, panel->hbp, panel->hsw);
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- debug("vfp=%d,vbp=%d,vsw=%d / clk-div=%d)\n",
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- panel->vfp, panel->vfp, panel->vsw, panel->pxl_clk_div);
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+ debug("vfp=%d,vbp=%d,vsw=%d / clk=%d)\n",
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+ panel->vfp, panel->vfp, panel->vsw, panel->pxl_clk);
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debug("using frambuffer at 0x%08x with size %d.\n",
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(unsigned int)gd->fb_base, FBSIZE(panel));
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+ /* setup display pll for requested clock frequency */
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+ err = panel->pxl_clk;
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+ err_r = err;
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+
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+ for (d = 2; d < 255; d++) {
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+ for (m = 2; m < 2047; m++) {
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+ if ((V_OSCK * m) < (panel->pxl_clk * d))
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+ continue;
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+ n = (V_OSCK * m) / (panel->pxl_clk * d);
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+ if (n > 127)
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+ break;
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+ if (((V_OSCK * m) / n) > LCDC_FMAX)
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+ break;
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+
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+ err = abs((V_OSCK * m) / n / d - panel->pxl_clk);
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+ if (err < err_r) {
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+ err_r = err;
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+ dpll_disp.m = m;
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+ dpll_disp.n = n;
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+ best_d = d;
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+ }
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+ }
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+ }
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+ debug("%s: PLL: best error %d Hz (M %d, N %d, DISP %d)\n",
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+ __func__, err_r, dpll_disp.m, dpll_disp.n, best_d);
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+ do_setup_dpll(&dpll_disp_regs, &dpll_disp);
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+
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+ /* clock source for LCDC from dispPLL M2 */
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+ writel(0x0, &cmdpll->clklcdcpixelclk);
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+
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/* palette default entry */
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memset((void *)gd->fb_base, 0, 0x20);
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*(unsigned int *)gd->fb_base = 0x4000;
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@@ -147,14 +195,14 @@ int am335xfb_init(struct am335x_lcdpanel *panel)
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gd->fb_base += 0x20;
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/* turn ON display through powercontrol function if accessible */
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- if (0 != panel->panel_power_ctrl)
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+ if (panel->panel_power_ctrl != NULL)
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panel->panel_power_ctrl(1);
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debug("am335x-fb: wait for stable power ...\n");
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mdelay(panel->pup_delay);
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lcdhw->clkc_enable = LCD_CORECLKEN | LCD_LIDDCLKEN | LCD_DMACLKEN;
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lcdhw->raster_ctrl = 0;
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- lcdhw->ctrl = LCD_CLK_DIVISOR(panel->pxl_clk_div) | LCD_RASTER_MODE;
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+ lcdhw->ctrl = LCD_CLK_DIVISOR(best_d) | LCD_RASTER_MODE;
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lcdhw->lcddma_fb0_base = gd->fb_base;
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lcdhw->lcddma_fb0_ceiling = gd->fb_base + FBSIZE(panel);
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lcdhw->lcddma_fb1_base = gd->fb_base;
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Tom Rini