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@@ -514,20 +514,17 @@ static u32 sdr_get_addr_rw(struct socfpga_sdram_config *cfg)
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return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
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}
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-/* Function to initialize SDRAM MMR */
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-unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
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+/**
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+ * sdr_load_regs() - Load SDRAM controller registers
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+ * @cfg: SDRAM controller configuration data
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+ *
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+ * This function loads the register values into the SDRAM controller block.
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+ */
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+static void sdr_load_regs(struct socfpga_sdram_config *cfg)
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{
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- unsigned long status = 0;
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- struct socfpga_sdram_config *cfg = &sdram_config;
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- const unsigned int rows =
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- (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
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- SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
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-
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const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
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const u32 dram_addrw = sdr_get_addr_rw(cfg);
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- writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
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-
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debug("\nConfiguring CTRLCFG\n");
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writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
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@@ -616,6 +613,20 @@ unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
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debug("Configuring DRAMODT\n");
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writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
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+}
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+
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+/* Function to initialize SDRAM MMR */
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+unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
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+{
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+ unsigned long status = 0;
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+ struct socfpga_sdram_config *cfg = &sdram_config;
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+ const unsigned int rows =
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+ (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
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+ SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
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+
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+ writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
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+
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+ sdr_load_regs(cfg);
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/* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
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writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
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