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@@ -740,7 +740,7 @@ struct mxc_ccm_reg {
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#define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
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#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
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#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
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-#ifdef CONFIG_MX6SX
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+/* The following *CCGR6* exist only i.MX6SX */
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#define MXC_CCM_CCGR6_PWM8_OFFSET 16
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#define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
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#define MXC_CCM_CCGR6_VADC_OFFSET 20
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@@ -755,10 +755,9 @@ struct mxc_ccm_reg {
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#define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
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#define MXC_CCM_CCGR6_PWM7_OFFSET 30
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#define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
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-#else
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+/* The two does not exist on i.MX6SX */
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#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
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#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
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-#endif
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#define BM_ANADIG_PLL_SYS_LOCK 0x80000000
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#define BP_ANADIG_PLL_SYS_RSVD0 20
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