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@@ -152,10 +152,10 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
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.emif_ddr_phy_ctlr_1_init = 0x0E24400A,
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.emif_ddr_phy_ctlr_1_init = 0x0E24400A,
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.emif_ddr_phy_ctlr_1 = 0x0E24400A,
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.emif_ddr_phy_ctlr_1 = 0x0E24400A,
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.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
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.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
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- .emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
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- .emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
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- .emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
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- .emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
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+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
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+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
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+ .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
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+ .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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@@ -177,10 +177,10 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
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.emif_ddr_phy_ctlr_1_init = 0x0E24400A,
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.emif_ddr_phy_ctlr_1_init = 0x0E24400A,
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.emif_ddr_phy_ctlr_1 = 0x0E24400A,
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.emif_ddr_phy_ctlr_1 = 0x0E24400A,
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.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
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.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
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- .emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
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- .emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
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- .emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
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- .emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
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+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
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+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
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+ .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
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+ .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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@@ -423,22 +423,22 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
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const u32
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const u32
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dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
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dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
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- 0x00BB00BB,
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- 0x00440044,
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- 0x00440044,
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- 0x00440044,
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- 0x00440044,
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- 0x00440044,
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+ 0x00980098,
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+ 0x00340034,
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+ 0x00350035,
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+ 0x00340034,
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+ 0x00310031,
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+ 0x00340034,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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- 0x00600060,
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- 0x00600060,
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- 0x00600060,
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- 0x00600060,
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- 0x00600060,
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+ 0x00480048,
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+ 0x004A004A,
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+ 0x00520052,
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+ 0x00550055,
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+ 0x00500050,
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0x00000000,
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0x00000000,
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0x00600020,
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0x00600020,
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0x40010080,
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0x40010080,
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@@ -452,22 +452,22 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
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const u32
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const u32
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dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
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dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
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- 0x00BB00BB,
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- 0x00440044,
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- 0x00440044,
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- 0x00440044,
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- 0x00440044,
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- 0x00440044,
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+ 0x00980098,
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+ 0x00330033,
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+ 0x00330033,
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+ 0x002F002F,
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+ 0x00320032,
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+ 0x00310031,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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- 0x00600060,
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- 0x00600060,
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- 0x00600060,
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- 0x00600060,
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- 0x00600060,
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+ 0x00520052,
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+ 0x00520052,
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+ 0x00470047,
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+ 0x00490049,
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+ 0x00500050,
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0x00000000,
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0x00000000,
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0x00600020,
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0x00600020,
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0x40010080,
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0x40010080,
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