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@@ -5,7 +5,9 @@
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*/
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#include <common.h>
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+#include <dm.h>
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#include <i2c.h>
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+#include <phy.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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@@ -22,6 +24,29 @@ DECLARE_GLOBAL_DATA_PTR;
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#define PINCTRL_NB_REG_VALUE 0x000173fa
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#define PINCTRL_SB_REG_VALUE 0x00007a23
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+/* Ethernet switch registers */
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+/* SMI addresses for multi-chip mode */
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+#define MVEBU_PORT_CTRL_SMI_ADDR(p) (16 + (p))
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+#define MVEBU_SW_G2_SMI_ADDR (28)
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+
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+/* Multi-chip mode */
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+#define MVEBU_SW_SMI_DATA_REG (1)
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+#define MVEBU_SW_SMI_CMD_REG (0)
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+ #define SW_SMI_CMD_REG_ADDR_OFF 0
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+ #define SW_SMI_CMD_DEV_ADDR_OFF 5
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+ #define SW_SMI_CMD_SMI_OP_OFF 10
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+ #define SW_SMI_CMD_SMI_MODE_OFF 12
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+ #define SW_SMI_CMD_SMI_BUSY_OFF 15
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+
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+/* Single-chip mode */
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+/* Switch Port Registers */
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+#define MVEBU_SW_LINK_CTRL_REG (1)
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+#define MVEBU_SW_PORT_CTRL_REG (4)
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+
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+/* Global 2 Registers */
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+#define MVEBU_G2_SMI_PHY_CMD_REG (24)
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+#define MVEBU_G2_SMI_PHY_DATA_REG (25)
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+
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int board_early_init_f(void)
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{
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const void *blob = gd->fdt_blob;
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@@ -156,3 +181,69 @@ int board_xhci_enable(void)
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return 0;
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}
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+
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+/* Helper function for accessing switch devices in multi-chip connection mode */
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+static int mii_multi_chip_mode_write(struct mii_dev *bus, int dev_smi_addr,
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+ int smi_addr, int reg, u16 value)
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+{
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+ u16 smi_cmd = 0;
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+
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+ if (bus->write(bus, dev_smi_addr, 0,
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+ MVEBU_SW_SMI_DATA_REG, value) != 0) {
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+ printf("Error writing to the PHY addr=%02x reg=%02x\n",
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+ smi_addr, reg);
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+ return -EFAULT;
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+ }
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+
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+ smi_cmd = (1 << SW_SMI_CMD_SMI_BUSY_OFF) |
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+ (1 << SW_SMI_CMD_SMI_MODE_OFF) |
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+ (1 << SW_SMI_CMD_SMI_OP_OFF) |
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+ (smi_addr << SW_SMI_CMD_DEV_ADDR_OFF) |
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+ (reg << SW_SMI_CMD_REG_ADDR_OFF);
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+ if (bus->write(bus, dev_smi_addr, 0,
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+ MVEBU_SW_SMI_CMD_REG, smi_cmd) != 0) {
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+ printf("Error writing to the PHY addr=%02x reg=%02x\n",
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+ smi_addr, reg);
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+ return -EFAULT;
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+ }
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+
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+ return 0;
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+}
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+
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+/* Bring-up board-specific network stuff */
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+int board_network_enable(struct mii_dev *bus)
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+{
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+ if (!of_machine_is_compatible("marvell,armada-3720-espressobin"))
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+ return 0;
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+
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+ /*
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+ * FIXME: remove this code once Topaz driver gets available
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+ * A3720 Community Board Only
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+ * Configure Topaz switch (88E6341)
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+ * Set port 0,1,2,3 to forwarding Mode (through Switch Port registers)
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+ */
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+ mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
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+ MVEBU_SW_PORT_CTRL_REG, 0x7f);
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+ mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
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+ MVEBU_SW_PORT_CTRL_REG, 0x7f);
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+ mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
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+ MVEBU_SW_PORT_CTRL_REG, 0x7f);
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+ mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
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+ MVEBU_SW_PORT_CTRL_REG, 0x7f);
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+
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+ /* RGMII Delay on Port 0 (CPU port), force link to 1000Mbps */
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+ mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
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+ MVEBU_SW_LINK_CTRL_REG, 0xe002);
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+
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+ /* Power up PHY 1, 2, 3 (through Global 2 registers) */
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+ mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
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+ MVEBU_G2_SMI_PHY_DATA_REG, 0x1140);
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+ mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
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+ MVEBU_G2_SMI_PHY_CMD_REG, 0x9620);
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+ mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
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+ MVEBU_G2_SMI_PHY_CMD_REG, 0x9640);
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+ mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
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+ MVEBU_G2_SMI_PHY_CMD_REG, 0x9660);
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+
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+ return 0;
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+}
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