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@@ -10,7 +10,7 @@
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#include <asm/secure.h>
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#include <asm/arch/imx-regs.h>
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#include <common.h>
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-
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+#include <fsl_wdog.h>
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#define GPC_CPU_PGC_SW_PDN_REQ 0xfc
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#define GPC_CPU_PGC_SW_PUP_REQ 0xf0
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@@ -26,6 +26,9 @@
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#define BP_SRC_A7RCR0_A7_CORE_RESET0 0
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#define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
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+#define CCM_ROOT_WDOG 0xbb80
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+#define CCM_CCGR_WDOG1 0x49c0
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+
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static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
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{
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writel(enable, GPC_IPS_BASE_ADDR + offset);
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@@ -74,3 +77,13 @@ __secure int imx_cpu_off(int cpu)
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writel(0, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D + 4);
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return 0;
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}
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+
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+__secure void imx_system_reset(void)
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+{
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+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
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+
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+ /* make sure WDOG1 clock is enabled */
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+ writel(0x1 << 28, CCM_BASE_ADDR + CCM_ROOT_WDOG);
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+ writel(0x3, CCM_BASE_ADDR + CCM_CCGR_WDOG1);
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+ writew(WCR_WDE, &wdog->wcr);
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+}
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