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@@ -970,22 +970,6 @@ struct mvpp2_bm_pool {
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int in_use_thresh;
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};
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-struct mvpp2_buff_hdr {
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- u32 next_buff_dma_addr;
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- u32 next_buff_virt_addr;
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- u16 byte_count;
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- u16 info;
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- u8 reserved1; /* bm_qset (for future use, BM) */
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-};
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-
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-/* Buffer header info bits */
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-#define MVPP2_B_HDR_INFO_MC_ID_MASK 0xfff
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-#define MVPP2_B_HDR_INFO_MC_ID(info) ((info) & MVPP2_B_HDR_INFO_MC_ID_MASK)
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-#define MVPP2_B_HDR_INFO_LAST_OFFS 12
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-#define MVPP2_B_HDR_INFO_LAST_MASK BIT(12)
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-#define MVPP2_B_HDR_INFO_IS_LAST(info) \
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- ((info & MVPP2_B_HDR_INFO_LAST_MASK) >> MVPP2_B_HDR_INFO_LAST_OFFS)
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-
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/* Static declaractions */
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/* Number of RXQs used by single port */
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@@ -3892,10 +3876,6 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
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pool = mvpp2_bm_cookie_pool_get(bm);
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bm_pool = &port->priv->bm_pools[pool];
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- /* Check if buffer header is used */
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- if (rx_status & MVPP2_RXD_BUF_HDR)
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- return 0;
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-
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/* In case of an error, release the requested buffer pointer
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* to the Buffer Manager. This request process is controlled
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* by the hardware, and the information about the buffer is
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