gpio: stm32_gpio: move clock config from driver to board

This patch removes the gpio clock enable from gpio driver & move it in the
board code, making it possible to use the gpio driver with other socs.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>

arch/arm/include/asm/arch-stm32f4/stm32_periph.h

@@ -22,6 +22,17 @@ enum periph_id {
 enum periph_clock {
 	USART1_CLOCK_CFG = 0,
 	USART2_CLOCK_CFG,
+	GPIO_A_CLOCK_CFG,
+	GPIO_B_CLOCK_CFG,
+	GPIO_C_CLOCK_CFG,
+	GPIO_D_CLOCK_CFG,
+	GPIO_E_CLOCK_CFG,
+	GPIO_F_CLOCK_CFG,
+	GPIO_G_CLOCK_CFG,
+	GPIO_H_CLOCK_CFG,
+	GPIO_I_CLOCK_CFG,
+	GPIO_J_CLOCK_CFG,
+	GPIO_K_CLOCK_CFG,
 };
 
 #endif /* __ASM_ARM_ARCH_PERIPH_H */

arch/arm/mach-stm32/stm32f4/clock.c

@@ -71,6 +71,21 @@
 #define FLASH_ACR_ICEN		(1 << 9)
 #define FLASH_ACR_DCEN		(1 << 10)
 
+/*
+ * RCC GPIO specific definitions
+ */
+#define RCC_ENR_GPIO_A_EN	(1 << 0)
+#define RCC_ENR_GPIO_B_EN	(1 << 1)
+#define RCC_ENR_GPIO_C_EN	(1 << 2)
+#define RCC_ENR_GPIO_D_EN	(1 << 3)
+#define RCC_ENR_GPIO_E_EN	(1 << 4)
+#define RCC_ENR_GPIO_F_EN	(1 << 5)
+#define RCC_ENR_GPIO_G_EN	(1 << 6)
+#define RCC_ENR_GPIO_H_EN	(1 << 7)
+#define RCC_ENR_GPIO_I_EN	(1 << 8)
+#define RCC_ENR_GPIO_J_EN	(1 << 9)
+#define RCC_ENR_GPIO_K_EN	(1 << 10)
+
 struct pll_psc {
 	u8	pll_m;
 	u16	pll_n;
@@ -237,6 +252,39 @@ void clock_setup(int peripheral)
 	case USART1_CLOCK_CFG:
 		setbits_le32(&STM32_RCC->apb2enr, RCC_ENR_USART1EN);
 		break;
+	case GPIO_A_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_A_EN);
+		break;
+	case GPIO_B_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_B_EN);
+		break;
+	case GPIO_C_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_C_EN);
+		break;
+	case GPIO_D_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_D_EN);
+		break;
+	case GPIO_E_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_E_EN);
+		break;
+	case GPIO_F_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_F_EN);
+		break;
+	case GPIO_G_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_G_EN);
+		break;
+	case GPIO_H_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_H_EN);
+		break;
+	case GPIO_I_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_I_EN);
+		break;
+	case GPIO_J_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_J_EN);
+		break;
+	case GPIO_K_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_K_EN);
+		break;
 	default:
 		break;
 	}

board/st/stm32f429-discovery/stm32f429-discovery.c

@@ -50,6 +50,7 @@ int uart_setup_gpio(void)
 	int i;
 	int rv = 0;
 
+	clock_setup(GPIO_A_CLOCK_CFG);
 	for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) {
 		rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart);
 		if (rv)
@@ -115,6 +116,13 @@ static int fmc_setup_gpio(void)
 	int rv = 0;
 	int i;
 
+	clock_setup(GPIO_B_CLOCK_CFG);
+	clock_setup(GPIO_C_CLOCK_CFG);
+	clock_setup(GPIO_D_CLOCK_CFG);
+	clock_setup(GPIO_E_CLOCK_CFG);
+	clock_setup(GPIO_F_CLOCK_CFG);
+	clock_setup(GPIO_G_CLOCK_CFG);
+
 	for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) {
 		rv = stm32_gpio_config(&ext_ram_fmc_gpio[i],
 				&gpio_ctl_fmc);

drivers/gpio/stm32_gpio.c

@@ -70,8 +70,6 @@ int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
 
 	gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
 
-	setbits_le32(&STM32_RCC->ahb1enr, 1 << dsc->port);
-
 	i = (dsc->pin & 0x07) * 4;
 	clrsetbits_le32(&gpio_regs->afr[dsc->pin >> 3], 0xF << i, ctl->af << i);
 
@@ -141,9 +139,6 @@ int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
 
 	gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
 
-	/* Enable clock for GPIO port */
-	setbits_le32(&STM32_RCC->apb2enr, 0x04 << dsc->port);
-
 	if (p < 8) {
 		cr = &gpio_regs->crl;
 		crp = p;