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@@ -37,6 +37,7 @@ void get_sys_info(sys_info_t *sys_info)
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
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#endif
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+ __maybe_unused u32 svr;
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const u8 core_cplx_PLL[16] = {
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[ 0] = 0, /* CC1 PPL / 1 */
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@@ -122,11 +123,27 @@ void get_sys_info(sys_info_t *sys_info)
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/* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
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* T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
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* it uses 6.
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+ * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
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*/
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#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
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- defined(CONFIG_PPC_T4080)
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- if (SVR_MAJ(get_svr()) >= 2)
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- mem_pll_rat *= 2;
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+ defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080)
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+ svr = get_svr();
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+ switch (SVR_SOC_VER(svr)) {
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+ case SVR_T4240:
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+ case SVR_T4160:
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+ case SVR_T4120:
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+ case SVR_T4080:
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+ if (SVR_MAJ(svr) >= 2)
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+ mem_pll_rat *= 2;
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+ break;
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+ case SVR_T2080:
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+ case SVR_T2081:
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+ if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1))
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+ mem_pll_rat *= 2;
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+ break;
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+ default:
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+ break;
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+ }
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#endif
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if (mem_pll_rat > 2)
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sys_info->freq_ddrbus *= mem_pll_rat;
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