Merge branch 'master' of git://git.denx.de/u-boot-uniphier

arch/arm/cpu/armv7/uniphier/Kconfig

@@ -5,15 +5,17 @@ config SYS_SOC
 	default "uniphier"
 
 config SYS_CONFIG_NAME
-	default "ph1_pro4" if MACH_PH1_PRO4
-	default "ph1_ld4" if MACH_PH1_LD4
-	default "ph1_sld8" if MACH_PH1_SLD8
+	default "uniphier"
+
+config UNIPHIER_SMP
+	bool
 
 choice
 	prompt "UniPhier SoC select"
 
 config MACH_PH1_PRO4
 	bool "PH1-Pro4"
+	select UNIPHIER_SMP
 
 config MACH_PH1_LD4
 	bool "PH1-LD4"
@@ -23,6 +25,29 @@ config MACH_PH1_SLD8
 
 endchoice
 
+choice
+	prompt "UniPhier Support Card select"
+	optional
+
+config PFC_MICRO_SUPPORT_CARD
+	bool "Support card with PFC CPLD"
+	help
+	  This option provides support for the expansion board with PFC
+	  original address mapping.
+
+	  Say Y to use the on-board UART, Ether, LED devices.
+
+config DCC_MICRO_SUPPORT_CARD
+	bool "Support card with DCC CPLD"
+	help
+	  This option provides support for the expansion board with DCC-
+	  arranged address mapping that is compatible with legacy UniPhier
+	  reference boards.
+
+	  Say Y to use the on-board UART, Ether, LED devices.
+
+endchoice
+
 config CMD_PINMON
 	bool "Enable boot mode pins monitor command"
 	depends on !SPL_BUILD

arch/arm/cpu/armv7/uniphier/Makefile

@@ -11,6 +11,7 @@ obj-y += cache_uniphier.o
 obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o
 obj-y += dram_init.o
 obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
+obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o
 obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
 obj-$(CONFIG_UNIPHIER_SMP) += smp.o
 obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o

arch/arm/cpu/armv7/uniphier/board_early_init_r.c

@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/board.h>
+
+int board_early_init_r(void)
+{
+	uniphier_board_late_init();
+	return 0;
+}

arch/arm/cpu/armv7/uniphier/board_late_init.c

@@ -26,42 +26,6 @@ static void nand_denali_wp_disable(void)
 #endif
 }
 
-static void nand_denali_fixup(void)
-{
-#if defined(CONFIG_NAND_DENALI) && \
-	(defined(CONFIG_MACH_PH1_SLD8) || defined(CONFIG_MACH_PH1_PRO4))
-	/*
-	 * The Denali NAND controller on some of UniPhier SoCs does not
-	 * automatically query the device parameters.  For those SoCs,
-	 * some registers must be set after the device is probed.
-	 */
-	void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
-	struct mtd_info *mtd;
-	struct nand_chip *chip;
-
-	if (nand_curr_device < 0 ||
-	    nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE) {
-		/* NAND was not detected. Just return. */
-		return;
-	}
-
-	mtd = &nand_info[nand_curr_device];
-	chip = mtd->priv;
-
-	writel(mtd->erasesize / mtd->writesize, denali_reg + PAGES_PER_BLOCK);
-	writel(0, denali_reg + DEVICE_WIDTH);
-	writel(mtd->writesize, denali_reg + DEVICE_MAIN_AREA_SIZE);
-	writel(mtd->oobsize, denali_reg + DEVICE_SPARE_AREA_SIZE);
-	writel(1, denali_reg + DEVICES_CONNECTED);
-
-	/*
-	 * chip->scan_bbt in nand_scan_tail() has been skipped.
-	 * It should be done in here.
-	 */
-	chip->scan_bbt(mtd);
-#endif
-}
-
 int board_late_init(void)
 {
 	puts("MODE:  ");
@@ -70,7 +34,6 @@ int board_late_init(void)
 	case BOOT_DEVICE_MMC1:
 		printf("eMMC Boot\n");
 		setenv("bootmode", "emmcboot");
-		nand_denali_fixup();
 		break;
 	case BOOT_DEVICE_NAND:
 		printf("NAND Boot\n");
@@ -80,7 +43,6 @@ int board_late_init(void)
 	case BOOT_DEVICE_NOR:
 		printf("NOR Boot\n");
 		setenv("bootmode", "norboot");
-		nand_denali_fixup();
 		break;
 	default:
 		printf("Unsupported Boot Mode\n");

arch/arm/cpu/armv7/uniphier/init_page_table.c

@@ -28,7 +28,12 @@
 #define IS_SSC(x)		((IS_SPL_TEXT_AREA(x)) || \
 					(IS_INIT_STACK_AREA(x)))
 #define IS_EXT(x)		((x) < 0x100)
-#define IS_REG(x)		(0x500 <= (x) && (x) < 0x700)
+
+/* 0x20000000-0x2fffffff, 0xf0000000-0xffffffff are only used by PH1-sLD3 */
+#define IS_REG(x)		(0x200 <= (x) && (x) < 0x300) || \
+				(0x500 <= (x) && (x) < 0x700) || \
+				(0xf00 <= (x))
+
 #define IS_DDR(x)		(0x800 <= (x) && (x) < 0xf00)
 
 #define MMU_FLAGS(x)		(IS_SSC(x)) ? SSC : \

arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c

@@ -22,16 +22,7 @@ void sbc_init(void)
 	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
 	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
 
-	if (readl(SBBASE0) & 0x1) {
-		/*
-		 * Boot Swap Off: boot from mask ROM
-		 * 0x00000000-0x01ffffff: mask ROM
-		 * 0x02000000-0x3effffff: memory bank (31MB)
-		 * 0x03f00000-0x3fffffff: peripherals (1MB)
-		 */
-		writel(0x0000be01, SBBASE0); /* dummy */
-		writel(0x0200be01, SBBASE1);
-	} else {
+	if (boot_is_swapped()) {
 		/*
 		 * Boot Swap On: boot from external NOR/SRAM
 		 * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
@@ -40,6 +31,15 @@ void sbc_init(void)
 		 * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
 		 */
 		writel(0x0000bc01, SBBASE0);
+	} else {
+		/*
+		 * Boot Swap Off: boot from mask ROM
+		 * 0x00000000-0x01ffffff: mask ROM
+		 * 0x02000000-0x3effffff: memory bank (31MB)
+		 * 0x03f00000-0x3fffffff: peripherals (1MB)
+		 */
+		writel(0x0000be01, SBBASE0); /* dummy */
+		writel(0x0200be01, SBBASE1);
 	}
 #elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
 #if !defined(CONFIG_SPL_BUILD)

arch/arm/cpu/armv7/uniphier/support_card.c

@@ -83,6 +83,12 @@ static int support_card_show_revision(void)
 }
 #endif
 
+int check_support_card(void)
+{
+	printf("SC:    Micro Support Card ");
+	return support_card_show_revision();
+}
+
 void support_card_init(void)
 {
 	/*
@@ -94,12 +100,6 @@ void support_card_init(void)
 	support_card_reset_deassert();
 }
 
-int check_support_card(void)
-{
-	printf("SC:    Micro Support Card ");
-	return support_card_show_revision();
-}
-
 #if defined(CONFIG_SMC911X)
 #include <netdev.h>
 
@@ -112,18 +112,14 @@ int board_eth_init(bd_t *bis)
 #if !defined(CONFIG_SYS_NO_FLASH)
 
 #include <mtd/cfi_flash.h>
+#include <asm/arch/sbc-regs.h>
 
-#if CONFIG_SYS_MAX_FLASH_BANKS > 1
-static phys_addr_t flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS] =
-					CONFIG_SYS_FLASH_BANKS_LIST;
+struct memory_bank {
+	phys_addr_t base;
+	unsigned long size;
+};
 
-phys_addr_t cfi_flash_bank_addr(int i)
-{
-	return flash_banks_list[i];
-}
-#endif
-
-int mem_is_flash(phys_addr_t base)
+static int mem_is_flash(const struct memory_bank *mem)
 {
 	const int loop = 128;
 	u32 *scratch_addr;
@@ -131,8 +127,9 @@ int mem_is_flash(phys_addr_t base)
 	int ret = 1;
 	int i;
 
-	scratch_addr = map_physmem(base + 0x01e00000,
-					sizeof(u32) * loop, MAP_NOCACHE);
+	/* just in case, use the tail of the memory bank */
+	scratch_addr = map_physmem(mem->base + mem->size - sizeof(u32) * loop,
+				   sizeof(u32) * loop, MAP_NOCACHE);
 
 	for (i = 0; i < loop; i++, scratch_addr++) {
 		saved_value = readl(scratch_addr);
@@ -150,31 +147,79 @@ int mem_is_flash(phys_addr_t base)
 	return ret;
 }
 
-int board_flash_wp_on(void)
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
+	/* {address, size} */
+static const struct memory_bank memory_banks_boot_swap_off[] = {
+	{0x02000000, 0x01f00000},
+};
+
+static const struct memory_bank memory_banks_boot_swap_on[] = {
+	{0x00000000, 0x01f00000},
+};
+#endif
+
+#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+static const struct memory_bank memory_banks_boot_swap_off[] = {
+	{0x04000000, 0x04000000},
+};
+
+static const struct memory_bank memory_banks_boot_swap_on[] = {
+	{0x00000000, 0x04000000},
+	{0x04000000, 0x04000000},
+};
+#endif
+
+static const struct memory_bank
+*flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT];
+
+phys_addr_t cfi_flash_bank_addr(int i)
 {
-	int i;
-	int ret = 1;
+	return flash_banks_list[i]->base;
+}
 
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		if (mem_is_flash(cfi_flash_bank_addr(i))) {
-			/*
-			 * We found at least one flash.
-			 * We need to return 0 and call flash_init().
-			 */
-			ret = 0;
-		}
-#if CONFIG_SYS_MAX_FLASH_BANKS > 1
-		else {
-			/*
-			 * We might have a SRAM here.
-			 * To prevent SRAM data from being destroyed,
-			 * we set dummy address (SDRAM).
-			 */
-			flash_banks_list[i] = 0x80000000 + 0x10000 * i;
+unsigned long cfi_flash_bank_size(int i)
+{
+	return flash_banks_list[i]->size;
+}
+
+static void detect_num_flash_banks(void)
+{
+	const struct memory_bank *memory_bank, *end;
+
+	cfi_flash_num_flash_banks = 0;
+
+	if (boot_is_swapped()) {
+		memory_bank = memory_banks_boot_swap_on;
+		end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_on);
+	} else {
+		memory_bank = memory_banks_boot_swap_off;
+		end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_off);
+	}
+
+	for (; memory_bank < end; memory_bank++) {
+		if (cfi_flash_num_flash_banks >=
+		    CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
+			break;
+
+		if (mem_is_flash(memory_bank)) {
+			flash_banks_list[cfi_flash_num_flash_banks] =
+								memory_bank;
+
+			debug("flash bank found: base = 0x%lx, size = 0x%lx\n",
+			      memory_bank->base, memory_bank->size);
+			cfi_flash_num_flash_banks++;
 		}
-#endif
 	}
 
-	return ret;
+	debug("number of flash banks: %d\n", cfi_flash_num_flash_banks);
+}
+#else /* ONFIG_SYS_NO_FLASH */
+void detect_num_flash_banks(void)
+{
+};
+#endif /* ONFIG_SYS_NO_FLASH */
+
+void support_card_late_init(void)
+{
+	detect_num_flash_banks();
 }
-#endif

arch/arm/dts/Makefile

@@ -33,6 +33,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra124-jetson-tk1.dtb \
 	tegra124-venice2.dtb
 dtb-$(CONFIG_ARCH_UNIPHIER) += \
+	uniphier-ph1-sld3-ref.dtb \
 	uniphier-ph1-pro4-ref.dtb \
 	uniphier-ph1-ld4-ref.dtb \
 	uniphier-ph1-sld8-ref.dtb

arch/arm/dts/uniphier-ph1-ld4-ref.dts

@@ -23,20 +23,39 @@
 		bootargs = "console=ttyPS0,115200 earlyprintk";
 		stdout-path = &uart0;
 	};
+
+	aliases {
+		uart0 = &uart0;
+		uart1 = &uart1;
+		uart2 = &uart2;
+		uart3 = &uart3;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+	};
 };
 
 &uart0 {
-       status = "okay";
+	status = "okay";
 };
 
 &uart1 {
-       status = "okay";
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	eeprom {
+		compatible = "i2c-eeprom";
+		reg = <0x50>;
+	};
 };
 
 &usb0 {
-      status = "okay";
+	status = "okay";
 };
 
 &usb1 {
-      status = "okay";
+	status = "okay";
 };

arch/arm/dts/uniphier-ph1-ld4.dtsi

@@ -13,8 +13,8 @@
 	compatible = "panasonic,ph1-ld4";
 
 	cpus {
-		#size-cells = <0>;
 		#address-cells = <1>;
+		#size-cells = <0>;
 
 		cpu@0 {
 			device_type = "cpu";
@@ -57,6 +57,42 @@
 			clock-frequency = <36864000>;
 		};
 
+		i2c0: i2c@58400000 {
+			compatible = "panasonic,uniphier-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x58400000 0x40>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@58480000 {
+			compatible = "panasonic,uniphier-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x58480000 0x40>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@58500000 {
+			compatible = "panasonic,uniphier-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x58500000 0x40>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@58580000 {
+			compatible = "panasonic,uniphier-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x58580000 0x40>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
 		usb0: usb@5a800100 {
 			compatible = "panasonic,uniphier-ehci", "usb-ehci";
 			status = "disabled";
@@ -74,5 +110,11 @@
 			status = "disabled";
 			reg = <0x5a820100 0x100>;
 		};
+
+		nand: nand@68000000 {
+			compatible = "denali,denali-nand-dt";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			reg-names = "nand_data", "denali_reg";
+		};
 	};
 };

arch/arm/dts/uniphier-ph1-pro4-ref.dts

@@ -23,20 +23,41 @@
 		bootargs = "console=ttyPS0,115200 earlyprintk";
 		stdout-path = &uart0;
 	};
+
+	aliases {
+		uart0 = &uart0;
+		uart1 = &uart1;
+		uart2 = &uart2;
+		uart3 = &uart3;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+	};
 };
 
 &uart0 {
-       status = "okay";
+	status = "okay";
 };
 
 &uart1 {
-       status = "okay";
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	eeprom {
+		compatible = "i2c-eeprom";
+		reg = <0x50>;
+	};
 };
 
 &usb0 {
-      status = "okay";
+	status = "okay";
 };
 
 &usb1 {
-      status = "okay";
+	status = "okay";
 };

arch/arm/dts/uniphier-ph1-pro4.dtsi

@@ -13,8 +13,8 @@
 	compatible = "panasonic,ph1-pro4";
 
 	cpus {
-		#size-cells = <0>;
 		#address-cells = <1>;
+		#size-cells = <0>;
 
 		cpu@0 {
 			device_type = "cpu";
@@ -63,6 +63,62 @@
 			clock-frequency = <73728000>;
 		};
 
+		i2c0: i2c@58780000 {
+			compatible = "panasonic,uniphier-fi2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x58780000 0x80>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@58781000 {
+			compatible = "panasonic,uniphier-fi2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x58781000 0x80>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@58782000 {
+			compatible = "panasonic,uniphier-fi2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x58782000 0x80>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@58783000 {
+			compatible = "panasonic,uniphier-fi2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x58783000 0x80>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		/* i2c4 does not exist */
+
+		i2c5: i2c@58785000 {
+			compatible = "panasonic,uniphier-fi2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x58785000 0x80>;
+			clock-frequency = <400000>;
+			status = "ok";
+		};
+
+		i2c6: i2c@58786000 {
+			compatible = "panasonic,uniphier-fi2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x58786000 0x80>;
+			clock-frequency = <400000>;
+			status = "ok";
+		};
+
 		usb0: usb@5a800100 {
 			compatible = "panasonic,uniphier-ehci", "usb-ehci";
 			status = "disabled";
@@ -74,5 +130,11 @@
 			status = "disabled";
 			reg = <0x5a810100 0x100>;
 		};
+
+		nand: nand@68000000 {
+			compatible = "denali,denali-nand-dt";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			reg-names = "nand_data", "denali_reg";
+		};
 	};
 };

arch/arm/dts/uniphier-ph1-sld3-ref.dts

@@ -0,0 +1,60 @@
+/*
+ * Device Tree Source for UniPhier PH1-sLD3 Reference Board
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-sld3.dtsi"
+
+/ {
+	model = "Panasonic UniPhier PH1-sLD3 Reference Board";
+	compatible = "panasonic,ph1-sld3-ref", "panasonic,ph1-sld3";
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyPS0,115200 earlyprintk";
+		stdout-path = &uart0;
+	};
+
+	aliases {
+		uart0 = &uart0;
+		uart1 = &uart1;
+		uart2 = &uart2;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	eeprom {
+		compatible = "i2c-eeprom";
+		reg = <0x50>;
+	};
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};

arch/arm/dts/uniphier-ph1-sld3.dtsi

@@ -0,0 +1,125 @@
+/*
+ * Device Tree Source for UniPhier PH1-sLD3 SoC
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "panasonic,ph1-sld3";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <1>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		uart0: serial@54006800 {
+			compatible = "panasonic,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006800 0x20>;
+			clock-frequency = <36864000>;
+		};
+
+		uart1: serial@54006900 {
+			compatible = "panasonic,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006900 0x20>;
+			clock-frequency = <36864000>;
+		};
+
+		uart2: serial@54006a00 {
+			compatible = "panasonic,uniphier-uart";
+			status = "disabled";
+			reg = <0x54006a00 0x20>;
+			clock-frequency = <36864000>;
+		};
+
+		i2c0: i2c@58400000 {
+			compatible = "panasonic,uniphier-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x58400000 0x40>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@58480000 {
+			compatible = "panasonic,uniphier-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x58480000 0x40>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@58500000 {
+			compatible = "panasonic,uniphier-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x58500000 0x40>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@58580000 {
+			compatible = "panasonic,uniphier-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x58580000 0x40>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		usb0: usb@5a800100 {
+			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			status = "disabled";
+			reg = <0x5a800100 0x100>;
+		};
+
+		usb1: usb@5a810100 {
+			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			status = "disabled";
+			reg = <0x5a810100 0x100>;
+		};
+
+		usb2: usb@5a820100 {
+			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			status = "disabled";
+			reg = <0x5a820100 0x100>;
+		};
+
+		usb3: usb@5a830100 {
+			compatible = "panasonic,uniphier-ehci", "usb-ehci";
+			status = "disabled";
+			reg = <0x5a830100 0x100>;
+		};
+
+		nand: nand@f8000000 {
+			compatible = "denali,denali-nand-dt";
+			reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
+			reg-names = "nand_data", "denali_reg";
+		};
+	};
+};

arch/arm/dts/uniphier-ph1-sld8-ref.dts

@@ -23,20 +23,39 @@
 		bootargs = "console=ttyPS0,115200 earlyprintk";
 		stdout-path = &uart0;
 	};
+
+	aliases {
+		uart0 = &uart0;
+		uart1 = &uart1;
+		uart2 = &uart2;
+		uart3 = &uart3;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+	};
 };
 
 &uart0 {
-       status = "okay";
+	status = "okay";
 };
 
 &uart1 {
-       status = "okay";
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	eeprom {
+		compatible = "i2c-eeprom";
+		reg = <0x50>;
+	};
 };
 
 &usb0 {
-      status = "okay";
+	status = "okay";
 };
 
 &usb1 {
-      status = "okay";
+	status = "okay";
 };

arch/arm/dts/uniphier-ph1-sld8.dtsi

@@ -13,8 +13,8 @@
 	compatible = "panasonic,ph1-sld8";
 
 	cpus {
-		#size-cells = <0>;
 		#address-cells = <1>;
+		#size-cells = <0>;
 
 		cpu@0 {
 			device_type = "cpu";
@@ -57,6 +57,42 @@
 			clock-frequency = <80000000>;
 		};
 
+		i2c0: i2c@58400000 {
+			compatible = "panasonic,uniphier-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x58400000 0x40>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@58480000 {
+			compatible = "panasonic,uniphier-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x58480000 0x40>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@58500000 {
+			compatible = "panasonic,uniphier-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x58500000 0x40>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@58580000 {
+			compatible = "panasonic,uniphier-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x58580000 0x40>;
+			clock-frequency = <100000>;
+			status = "disabled";
+		};
+
 		usb0: usb@5a800100 {
 			compatible = "panasonic,uniphier-ehci", "usb-ehci";
 			status = "disabled";
@@ -74,5 +110,11 @@
 			status = "disabled";
 			reg = <0x5a820100 0x100>;
 		};
+
+		nand: nand@68000000 {
+			compatible = "denali,denali-nand-dt";
+			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+			reg-names = "nand_data", "denali_reg";
+		};
 	};
 };

arch/arm/include/asm/arch-uniphier/board.h

@@ -12,10 +12,12 @@
 	defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
 void support_card_reset(void);
 void support_card_init(void);
+void support_card_late_init(void);
 int check_support_card(void);
 #else
 #define support_card_reset() do {} while (0)
 #define support_card_init()  do {} while (0)
+#define support_card_late_init()  do {} while (0)
 static inline int check_support_card(void)
 {
 	return 0;
@@ -32,4 +34,9 @@ static inline void uniphier_board_init(void)
 	support_card_init();
 }
 
+static inline void uniphier_board_late_init(void)
+{
+	support_card_late_init();
+}
+
 #endif /* ARCH_BOARD_H */

common/board_r.c

@@ -291,26 +291,14 @@ static int initr_flash(void)
 {
 	ulong flash_size = 0;
 	bd_t *bd = gd->bd;
-	int ok;
 
 	puts("Flash: ");
 
-	if (board_flash_wp_on()) {
+	if (board_flash_wp_on())
 		printf("Uninitialized - Write Protect On\n");
-		/* Since WP is on, we can't find real size.  Set to 0 */
-		ok = 1;
-	} else {
+	else
 		flash_size = flash_init();
-		ok = flash_size > 0;
-	}
-	if (!ok) {
-		puts("*** failed ***\n");
-#ifdef CONFIG_PPC
-		/* Why does PPC do this? */
-		hang();
-#endif
-		return -1;
-	}
+
 	print_size(flash_size, "");
 #ifdef CONFIG_SYS_FLASH_CHECKSUM
 	/*

configs/ph1_ld4_defconfig

@@ -4,6 +4,7 @@ CONFIG_FIT_VERBOSE=y
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_UNIPHIER=y
 +S:CONFIG_MACH_PH1_LD4=y
++S:CONFIG_DCC_MICRO_SUPPORT_CARD=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BDI=y
 CONFIG_CMD_CONSOLE=y

configs/ph1_pro4_defconfig

@@ -4,6 +4,7 @@ CONFIG_FIT_VERBOSE=y
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_UNIPHIER=y
 +S:CONFIG_MACH_PH1_PRO4=y
++S:CONFIG_DCC_MICRO_SUPPORT_CARD=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BDI=y
 CONFIG_CMD_CONSOLE=y

configs/ph1_sld8_defconfig

@@ -4,6 +4,7 @@ CONFIG_FIT_VERBOSE=y
 +S:CONFIG_ARM=y
 +S:CONFIG_ARCH_UNIPHIER=y
 +S:CONFIG_MACH_PH1_SLD8=y
++S:CONFIG_DCC_MICRO_SUPPORT_CARD=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BDI=y
 CONFIG_CMD_CONSOLE=y

include/configs/ph1_ld4.h

@@ -1,53 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __PH1_XXX_H
-#define __PH1_XXX_H
-
-/*
- * Support Card Select
- *
- *  CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
- *  CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
- *                       CPLD is re-programmed for ARIMA board compatibility.
- *  No define                     - No support card.
- */
-
-#if 0
-#define CONFIG_PFC_MICRO_SUPPORT_CARD
-#else
-#define CONFIG_DCC_MICRO_SUPPORT_CARD
-#endif
-
-/*
- * Serial Configuration
- *   SoC UART     : enable CONFIG_UNIPHIER_SERIAL
- *   On-board UART: enable CONFIG_SYS_NS16550_SERIAL
- */
-#if 0
-#define CONFIG_SYS_NS16550_SERIAL
-#endif
-
-#define CONFIG_SMC911X
-
-#define CONFIG_DDR_NUM_CH0 1
-#define CONFIG_DDR_NUM_CH1 1
-
-/*
- * Memory Size & Mapping
- */
-/* Physical start address of SDRAM */
-#define CONFIG_SDRAM0_BASE	0x80000000
-#define CONFIG_SDRAM0_SIZE	0x10000000
-#define CONFIG_SDRAM1_BASE	0x90000000
-#define CONFIG_SDRAM1_SIZE	0x10000000
-
-#define CONFIG_SPL_TEXT_BASE 0x40000
-
-#include "uniphier-common.h"
-
-#endif /* __PH1_XXX_H */

include/configs/ph1_pro4.h

@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __PH1_XXX_H
-#define __PH1_XXX_H
-
-/*
- * Support Card Select
- *
- *  CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
- *  CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
- *                       CPLD is re-programmed for ARIMA board compatibility.
- *  No define                     - No support card.
- */
-
-#if 0
-#define CONFIG_PFC_MICRO_SUPPORT_CARD
-#else
-#define CONFIG_DCC_MICRO_SUPPORT_CARD
-#endif
-
-/*
- * Serial Configuration
- *   SoC UART     : enable CONFIG_UNIPHIER_SERIAL
- *   On-board UART: enable CONFIG_SYS_NS16550_SERIAL
- */
-#if 0
-#define CONFIG_SYS_NS16550_SERIAL
-#endif
-
-#define CONFIG_SMC911X
-
-#define CONFIG_DDR_NUM_CH0 2
-#define CONFIG_DDR_NUM_CH1 2
-
-#define CONFIG_UNIPHIER_SMP
-
-/*
- * Memory Size & Mapping
- */
-/* Physical start address of SDRAM */
-#define CONFIG_SDRAM0_BASE	0x80000000
-#define CONFIG_SDRAM0_SIZE	0x20000000
-#define CONFIG_SDRAM1_BASE	0xa0000000
-#define CONFIG_SDRAM1_SIZE	0x20000000
-
-#define CONFIG_SPL_TEXT_BASE 0x100000
-
-#include "uniphier-common.h"
-
-#endif /* __PH1_XXX_H */

include/configs/ph1_sld8.h

@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __PH1_XXX_H
-#define __PH1_XXX_H
-
-/*
- * Support Card Select
- *
- *  CONFIG_PFC_MICRO_SUPPORT_CARD - Original Micro Support Card made by PFC.
- *  CONFIG_DCC_MICRO_SUPPORT_CARD - DCC version Micro Support Card.
- *                       CPLD is re-programmed for ARIMA board compatibility.
- *  No define                     - No support card.
- */
-
-#if 0
-#define CONFIG_PFC_MICRO_SUPPORT_CARD
-#else
-#define CONFIG_DCC_MICRO_SUPPORT_CARD
-#endif
-
-/*
- * Serial Configuration
- *   SoC UART     : enable CONFIG_UNIPHIER_SERIAL
- *   On-board UART: enable CONFIG_SYS_NS16550_SERIAL
- */
-#if 0
-#define CONFIG_SYS_NS16550_SERIAL
-#endif
-
-#define CONFIG_SMC911X
-
-#define CONFIG_DDR_NUM_CH0 1
-#define CONFIG_DDR_NUM_CH1 1
-
-/* #define CONFIG_DDR_STANDARD */
-
-/*
- * Memory Size & Mapping
- */
-/* Physical start address of SDRAM */
-#define CONFIG_SDRAM0_BASE	0x80000000
-#define CONFIG_SDRAM0_SIZE	0x10000000
-#define CONFIG_SDRAM1_BASE	0x90000000
-#define CONFIG_SDRAM1_SIZE	0x10000000
-
-#define CONFIG_SPL_TEXT_BASE 0x40000
-
-#include "uniphier-common.h"
-
-#endif /* __PH1_XXX_H */

include/configs/uniphier-common.h → include/configs/uniphier.h

@@ -10,10 +10,37 @@
 #ifndef __CONFIG_UNIPHIER_COMMON_H__
 #define __CONFIG_UNIPHIER_COMMON_H__
 
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) &&	\
-				defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-# error "Both CONFIG_PFC_MICRO_SUPPORT_CARD and CONFIG_DCC_MICRO_SUPPORT_CARD \
-are defined. Select only one of them."
+#if defined(CONFIG_MACH_PH1_PRO4)
+#define CONFIG_DDR_NUM_CH0 2
+#define CONFIG_DDR_NUM_CH1 2
+
+/* Physical start address of SDRAM */
+#define CONFIG_SDRAM0_BASE	0x80000000
+#define CONFIG_SDRAM0_SIZE	0x20000000
+#define CONFIG_SDRAM1_BASE	0xa0000000
+#define CONFIG_SDRAM1_SIZE	0x20000000
+#endif
+
+#if defined(CONFIG_MACH_PH1_LD4)
+#define CONFIG_DDR_NUM_CH0 1
+#define CONFIG_DDR_NUM_CH1 1
+
+/* Physical start address of SDRAM */
+#define CONFIG_SDRAM0_BASE	0x80000000
+#define CONFIG_SDRAM0_SIZE	0x10000000
+#define CONFIG_SDRAM1_BASE	0x90000000
+#define CONFIG_SDRAM1_SIZE	0x10000000
+#endif
+
+#if defined(CONFIG_MACH_PH1_SLD8)
+#define CONFIG_DDR_NUM_CH0 1
+#define CONFIG_DDR_NUM_CH1 1
+
+/* Physical start address of SDRAM */
+#define CONFIG_SDRAM0_BASE	0x80000000
+#define CONFIG_SDRAM0_SIZE	0x10000000
+#define CONFIG_SDRAM1_BASE	0x90000000
+#define CONFIG_SDRAM1_SIZE	0x10000000
 #endif
 
 /*
@@ -40,6 +67,13 @@ are defined. Select only one of them."
 #define CONFIG_SYS_NS16550_REG_SIZE	-2
 #endif
 
+/* TODO: move to Kconfig and device tree */
+#if 0
+#define CONFIG_SYS_NS16550_SERIAL
+#endif
+
+#define CONFIG_SMC911X
+
 #define CONFIG_SMC911X_BASE		CONFIG_SUPPORT_CARD_ETHER_BASE
 #define CONFIG_SMC911X_32_BIT
 
@@ -58,6 +92,7 @@ are defined. Select only one of them."
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_BOARD_LATE_INIT
 
 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
@@ -87,17 +122,7 @@ are defined. Select only one of them."
 
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
-# define CONFIG_SYS_MAX_FLASH_BANKS	1
-# define CONFIG_SYS_FLASH_BANKS_LIST	{0x00000000}
-# define CONFIG_SYS_FLASH_BANKS_SIZES	{0x02000000}
-#endif
-
-#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-# define CONFIG_SYS_MAX_FLASH_BANKS	1
-# define CONFIG_SYS_FLASH_BANKS_LIST	{0x04000000}
-# define CONFIG_SYS_FLASH_BANKS_SIZES	{0x04000000}
-#endif
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
 
 /* serial console configuration */
 #define CONFIG_BAUDRATE			115200
@@ -205,7 +230,6 @@ are defined. Select only one of them."
 	"image_offset=0x00080000\0"		\
 	"image_size=0x00f00000\0"		\
 	"verify=n\0"				\
-	"autostart=yes\0"			\
 	"norboot=run add_default_bootargs;"				\
 		"bootm $image_offset\0"					\
 	"nandboot=run add_default_bootargs;"				\
@@ -233,6 +257,13 @@ are defined. Select only one of them."
 
 #define CONFIG_SYS_TEXT_BASE		0x84000000
 
+#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
+#define CONFIG_SPL_TEXT_BASE		0x00040000
+#endif
+#if defined(CONFIG_MACH_PH1_PRO4)
+#define CONFIG_SPL_TEXT_BASE		0x00100000
+#endif
+
 #define CONFIG_BOARD_POSTCLK_INIT
 
 #ifndef CONFIG_SPL_BUILD