imx: mx6: fix mmdc ch0 clk for 6SL

>From RM, per_periph2_clk_sel option3 is:
"derive clock from 198MHz clock (divided 392MHz PLL2 PFD)."

So fix it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

arch/arm/cpu/armv7/mx6/clock.c

@@ -514,6 +514,11 @@ static u32 get_mmdc_ch0_clk(void)
 				freq = mxc_get_pll_pfd(PLL_BUS, 0);
 				break;
 			case 3:
+				if (is_mx6sl()) {
+					freq = mxc_get_pll_pfd(PLL_BUS, 2) >> 1;
+					break;
+				}
+
 				pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
 				switch (pmu_misc2_audio_div) {
 				case 0: