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@@ -53,66 +53,66 @@ DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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- gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
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+ gd->ram_size = imx_ddr_size();
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return 0;
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}
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static iomux_v3_cfg_t const uart1_pads[] = {
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- MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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- MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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+ IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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+ IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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};
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static iomux_v3_cfg_t const usdhc1_pads[] = {
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- MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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+ IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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+ IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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+ IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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+ IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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+ IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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/* Carrier MicroSD Card Detect */
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- MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
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+ IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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static iomux_v3_cfg_t const usdhc3_pads[] = {
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- MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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- MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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+ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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+ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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+ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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+ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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+ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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/* SOM MicroSD Card Detect */
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- MX6_PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
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+ IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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static iomux_v3_cfg_t const enet_pads[] = {
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- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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- MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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/* AR8031 PHY Reset */
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- MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
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+ IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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static void setup_iomux_uart(void)
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{
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- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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+ SETUP_IOMUX_PADS(uart1_pads);
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}
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static void setup_iomux_enet(void)
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{
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- imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
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+ SETUP_IOMUX_PADS(enet_pads);
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/* Reset AR8031 PHY */
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gpio_direction_output(ETH_PHY_RESET, 0);
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@@ -156,15 +156,13 @@ int board_mmc_init(bd_t *bis)
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for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
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switch (index) {
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case 0:
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- imx_iomux_v3_setup_multiple_pads(
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- usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
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+ SETUP_IOMUX_PADS(usdhc3_pads);
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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usdhc_cfg[0].max_bus_width = 4;
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gpio_direction_input(USDHC3_CD_GPIO);
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break;
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case 1:
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- imx_iomux_v3_setup_multiple_pads(
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- usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
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+ SETUP_IOMUX_PADS(usdhc1_pads);
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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usdhc_cfg[1].max_bus_width = 4;
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gpio_direction_input(USDHC1_CD_GPIO);
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@@ -218,54 +216,66 @@ int board_phy_config(struct phy_device *phydev)
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}
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#if defined(CONFIG_VIDEO_IPUV3)
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-struct i2c_pads_info i2c2_pad_info = {
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+struct i2c_pads_info mx6q_i2c2_pad_info = {
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.scl = {
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- .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
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+ .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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- .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
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+ .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gp = IMX_GPIO_NR(4, 12)
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},
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.sda = {
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- .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
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+ .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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- .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
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+ .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
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+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
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+ .gp = IMX_GPIO_NR(4, 13)
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+ }
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+};
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+
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+struct i2c_pads_info mx6dl_i2c2_pad_info = {
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+ .scl = {
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+ .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
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+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
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+ .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
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+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
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+ .gp = IMX_GPIO_NR(4, 12)
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+ },
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+ .sda = {
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+ .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
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+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
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+ .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gp = IMX_GPIO_NR(4, 13)
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}
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};
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static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
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- MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
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- MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSync */
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- MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSync */
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- MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04
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- | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm), /* Contrast */
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- MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* DISP0_DRDY */
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-
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- MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
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- MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
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- MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
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- MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
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- MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
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- MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
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- MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
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- MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
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- MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
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- MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
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- MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
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- MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
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- MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
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- MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
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- MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
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- MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
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- MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
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- MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
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-
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- MX6_PAD_SD4_DAT2__GPIO2_IO10
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- | MUX_PAD_CTRL(NO_PAD_CTRL), /* DISP0_BKLEN */
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- MX6_PAD_SD4_DAT3__GPIO2_IO11
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- | MUX_PAD_CTRL(NO_PAD_CTRL), /* DISP0_VDDEN */
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+ IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
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+ IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
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+ IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
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+ IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
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+ IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
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+ IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
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+ IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
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+ IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
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+ IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
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+ IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
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+ IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
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+ IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
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+ IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
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+ IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
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+ IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
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+ IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
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+ IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
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+ IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
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+ IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
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+ IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
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+ IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
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+ IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
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+ IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
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+ IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
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+ IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
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};
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static void do_enable_hdmi(struct display_info_t const *dev)
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@@ -281,9 +291,7 @@ static int detect_i2c(struct display_info_t const *dev)
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static void enable_fwadapt_7wvga(struct display_info_t const *dev)
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{
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- imx_iomux_v3_setup_multiple_pads(
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- fwadapt_7wvga_pads,
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- ARRAY_SIZE(fwadapt_7wvga_pads));
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+ SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
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gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
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gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
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@@ -346,7 +354,7 @@ static void setup_display(void)
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writel(reg, &mxc_ccm->chsccdr);
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/* Disable LCD backlight */
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- imx_iomux_v3_setup_pad(MX6_PAD_DI0_PIN4__GPIO4_IO20);
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+ SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
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gpio_direction_input(IMX_GPIO_NR(4, 20));
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}
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#endif /* CONFIG_VIDEO_IPUV3 */
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@@ -391,6 +399,12 @@ int board_late_init(void)
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add_board_boot_modes(board_boot_modes);
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#endif
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+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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+ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
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+ setenv("board_rev", "MX6Q");
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+ else
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+ setenv("board_rev", "MX6DL");
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+#endif
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return 0;
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}
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@@ -399,7 +413,11 @@ int board_init(void)
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c2_pad_info);
|
|
|
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
|
|
|
+ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
|
|
|
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
|
|
|
+ else
|
|
|
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
|
|
|
|
|
|
return 0;
|
|
|
}
|