|
@@ -91,6 +91,15 @@
|
|
|
status = "okay";
|
|
|
};
|
|
|
|
|
|
+&usdhc2 {
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&pinctrl_usdhc2>;
|
|
|
+ cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
|
|
|
+ bus-width = <8>;
|
|
|
+ no-1-8-v;
|
|
|
+ status = "disabled";
|
|
|
+};
|
|
|
+
|
|
|
&iomuxc {
|
|
|
pinctrl_enet1: enet1grp {
|
|
|
fsl,pins = <
|
|
@@ -139,4 +148,21 @@
|
|
|
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
|
|
|
>;
|
|
|
};
|
|
|
+
|
|
|
+ pinctrl_usdhc2: usdhc2grp {
|
|
|
+ u-boot,dm-spl;
|
|
|
+ fsl,pins = <
|
|
|
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070
|
|
|
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070
|
|
|
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17070
|
|
|
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17070
|
|
|
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17070
|
|
|
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17070
|
|
|
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17070
|
|
|
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17070
|
|
|
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17070
|
|
|
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17070
|
|
|
+ MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17070
|
|
|
+ >;
|
|
|
+ };
|
|
|
};
|