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@@ -48,10 +48,16 @@ static void uart_zynq_serial_setbrg(const int port)
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/* Calculation results. */
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unsigned int calc_bauderror, bdiv, bgen;
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unsigned long calc_baud = 0;
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- unsigned long baud = gd->baudrate;
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+ unsigned long baud;
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unsigned long clock = get_uart_clk(port);
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struct uart_zynq *regs = uart_zynq_ports[port];
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+ /* Covering case where input clock is so slow */
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+ if (clock < 1000000 && gd->baudrate > 4800)
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+ gd->baudrate = 4800;
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+
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+ baud = gd->baudrate;
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+
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/* master clock
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* Baud rate = ------------------
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* bgen * (bdiv + 1)
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