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+/*
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+ * (C) Copyright 2012
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+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
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+ *
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+ * See file CREDITS for list of people who contributed to this
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+ * project.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of
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+ * the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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+ * MA 02111-1307 USA
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+ */
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+
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+#include <common.h>
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+#include <asm/io.h>
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+#include <errno.h>
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+
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+#include <gdsys_fpga.h>
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+
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+enum {
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+ MCINT_SLAVE_LINK_CHANGED_EV = 1 << 7,
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+ MCINT_TX_ERROR_EV = 1 << 9,
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+ MCINT_TX_BUFFER_FREE = 1 << 10,
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+ MCINT_TX_PACKET_TRANSMITTED_EV = 1 << 11,
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+ MCINT_RX_ERROR_EV = 1 << 13,
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+ MCINT_RX_CONTENT_AVAILABLE = 1 << 14,
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+ MCINT_RX_PACKET_RECEIVED_EV = 1 << 15,
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+};
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+
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+int mclink_probe(void)
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+{
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+ unsigned int k;
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+ int slaves = 0;
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+
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+ for (k = 0; k < CONFIG_SYS_MCLINK_MAX; ++k) {
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+ int timeout = 0;
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+ unsigned int ctr = 0;
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+ u16 mc_status;
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+
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+ FPGA_GET_REG(k, mc_status, &mc_status);
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+
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+ if (!(mc_status & (1 << 15)))
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+ break;
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+
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+ FPGA_SET_REG(k, mc_control, 0x8000);
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+
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+ FPGA_GET_REG(k, mc_status, &mc_status);
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+ while (!(mc_status & (1 << 14))) {
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+ udelay(100);
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+ if (ctr++ > 500) {
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+ timeout = 1;
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+ break;
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+ }
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+ FPGA_GET_REG(k, mc_status, &mc_status);
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+ }
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+ if (timeout)
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+ break;
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+
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+ printf("waited %d us for mclink %d to come up\n", ctr * 100, k);
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+
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+ slaves++;
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+ }
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+
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+ return slaves;
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+}
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+
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+int mclink_send(u8 slave, u16 addr, u16 data)
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+{
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+ unsigned int ctr = 0;
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+ u16 int_status;
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+ u16 rx_cmd_status;
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+ u16 rx_cmd;
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+
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+ /* reset interrupt status */
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+ FPGA_GET_REG(0, mc_int, &int_status);
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+ FPGA_SET_REG(0, mc_int, int_status);
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+
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+ /* send */
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+ FPGA_SET_REG(0, mc_tx_address, addr);
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+ FPGA_SET_REG(0, mc_tx_data, data);
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+ FPGA_SET_REG(0, mc_tx_cmd, (slave & 0x03) << 14);
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+ FPGA_SET_REG(0, mc_control, 0x8001);
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+
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+ /* wait for reply */
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+ FPGA_GET_REG(0, mc_int, &int_status);
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+ while (!(int_status & MCINT_RX_PACKET_RECEIVED_EV)) {
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+ udelay(100);
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+ if (ctr++ > 3)
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+ return -ETIMEDOUT;
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+ FPGA_GET_REG(0, mc_int, &int_status);
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+ }
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+
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+ FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status);
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+ rx_cmd = (rx_cmd_status >> 12) & 0x03;
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+ if (rx_cmd != 0)
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+ printf("mclink_send: received cmd %d, expected %d\n", rx_cmd,
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+ 0);
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+
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+ return 0;
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+}
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+
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+int mclink_receive(u8 slave, u16 addr, u16 *data)
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+{
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+ u16 rx_cmd_status;
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+ u16 rx_cmd;
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+ u16 int_status;
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+ unsigned int ctr = 0;
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+
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+ /* send read request */
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+ FPGA_SET_REG(0, mc_tx_address, addr);
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+ FPGA_SET_REG(0, mc_tx_cmd,
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+ ((slave & 0x03) << 14) | (1 << 12) | (1 << 0));
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+ FPGA_SET_REG(0, mc_control, 0x8001);
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+
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+
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+ /* wait for reply */
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+ FPGA_GET_REG(0, mc_int, &int_status);
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+ while (!(int_status & MCINT_RX_CONTENT_AVAILABLE)) {
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+ udelay(100);
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+ if (ctr++ > 3)
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+ return -ETIMEDOUT;
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+ FPGA_GET_REG(0, mc_int, &int_status);
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+ }
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+
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+ /* check reply */
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+ FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status);
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+ if ((rx_cmd_status >> 14) != slave) {
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+ printf("mclink_receive: reply from slave %d, expected %d\n",
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+ rx_cmd_status >> 14, slave);
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+ return -EINVAL;
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+ }
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+
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+ rx_cmd = (rx_cmd_status >> 12) & 0x03;
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+ if (rx_cmd != 1) {
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+ printf("mclink_send: received cmd %d, expected %d\n",
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+ rx_cmd, 1);
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+ return -EIO;
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+ }
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+
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+ FPGA_GET_REG(0, mc_rx_data, data);
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+
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+ return 0;
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+}
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