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@@ -1,354 +0,0 @@
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-/*
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- * Freescale Coldfire Queued SPI driver
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- *
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- * NOTE:
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- * This driver is written to transfer 8 bit at-a-time and uses the dedicated
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- * SPI slave select pins as bit-banged GPIO to work with spi_flash subsystem.
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- *
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- * Copyright (C) 2011 Ruggedcom, Inc.
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- * Richard Retanubun (richardretanubun@freescale.com)
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- *
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- * SPDX-License-Identifier: GPL-2.0+
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- */
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-
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-#include <common.h>
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-#include <malloc.h>
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-#include <spi.h>
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-#include <asm/immap.h>
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-#include <asm/io.h>
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-
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-DECLARE_GLOBAL_DATA_PTR;
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-
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-#define to_cf_qspi_slave(s) container_of(s, struct cf_qspi_slave, slave)
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-
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-struct cf_qspi_slave {
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- struct spi_slave slave; /* Specific bus:cs ID for each device */
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- qspi_t *regs; /* Pointer to SPI controller registers */
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- u16 qmr; /* QMR: Queued Mode Register */
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- u16 qwr; /* QWR: Queued Wrap Register */
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- u16 qcr; /* QCR: Queued Command Ram */
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-};
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-
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-/* Register write wrapper functions */
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-static void write_qmr(volatile qspi_t *qspi, u16 val) { qspi->mr = val; }
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-static void write_qdlyr(volatile qspi_t *qspi, u16 val) { qspi->dlyr = val; }
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-static void write_qwr(volatile qspi_t *qspi, u16 val) { qspi->wr = val; }
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-static void write_qir(volatile qspi_t *qspi, u16 val) { qspi->ir = val; }
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-static void write_qar(volatile qspi_t *qspi, u16 val) { qspi->ar = val; }
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-static void write_qdr(volatile qspi_t *qspi, u16 val) { qspi->dr = val; }
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-/* Register read wrapper functions */
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-static u16 read_qdlyr(volatile qspi_t *qspi) { return qspi->dlyr; }
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-static u16 read_qwr(volatile qspi_t *qspi) { return qspi->wr; }
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-static u16 read_qir(volatile qspi_t *qspi) { return qspi->ir; }
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-static u16 read_qdr(volatile qspi_t *qspi) { return qspi->dr; }
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-
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-/* These call points may be different for each ColdFire CPU */
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-extern void cfspi_port_conf(void);
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-static void cfspi_cs_activate(uint bus, uint cs, uint cs_active_high);
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-static void cfspi_cs_deactivate(uint bus, uint cs, uint cs_active_high);
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-
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-int spi_claim_bus(struct spi_slave *slave)
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-{
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- return 0;
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-}
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-void spi_release_bus(struct spi_slave *slave)
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-{
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-}
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-
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-__attribute__((weak))
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-void spi_init(void)
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-{
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- cfspi_port_conf();
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-}
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-
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-__attribute__((weak))
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-void spi_cs_activate(struct spi_slave *slave)
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-{
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- struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
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-
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- cfspi_cs_activate(slave->bus, slave->cs, !(dev->qwr & QSPI_QWR_CSIV));
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-}
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-
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-__attribute__((weak))
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-void spi_cs_deactivate(struct spi_slave *slave)
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-{
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- struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
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-
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- cfspi_cs_deactivate(slave->bus, slave->cs, !(dev->qwr & QSPI_QWR_CSIV));
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-}
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-
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-__attribute__((weak))
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-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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-{
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- /* Only 1 bus and 4 chipselect per controller */
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- if (bus == 0 && (cs >= 0 && cs < 4))
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- return 1;
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- else
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- return 0;
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-}
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-
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-void spi_free_slave(struct spi_slave *slave)
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-{
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- struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
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-
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- free(dev);
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-}
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-
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-/* Translate information given by spi_setup_slave to members of cf_qspi_slave */
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-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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- unsigned int max_hz, unsigned int mode)
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-{
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- struct cf_qspi_slave *dev = NULL;
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-
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- if (!spi_cs_is_valid(bus, cs))
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- return NULL;
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-
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- dev = spi_alloc_slave(struct cf_qspi_slave, bus, cs);
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- if (!dev)
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- return NULL;
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-
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- /* Initialize to known value */
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- dev->regs = (qspi_t *)MMAP_QSPI;
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- dev->qmr = 0;
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- dev->qwr = 0;
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- dev->qcr = 0;
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-
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-
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- /* Map max_hz to QMR[BAUD] */
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- if (max_hz == 0) /* Go as fast as possible */
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- dev->qmr = 2u;
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- else /* Get the closest baud rate */
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- dev->qmr = clamp(((gd->bus_clk >> 2) + max_hz - 1)/max_hz,
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- 2lu, 255lu);
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-
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- /* Map mode to QMR[CPOL] and QMR[CPHA] */
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- if (mode & SPI_CPOL)
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- dev->qmr |= QSPI_QMR_CPOL;
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-
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- if (mode & SPI_CPHA)
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- dev->qmr |= QSPI_QMR_CPHA;
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-
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- /* Hardcode bit length to 8 bit per transter */
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- dev->qmr |= QSPI_QMR_BITS_8;
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-
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- /* Set QMR[MSTR] to enable QSPI as master */
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- dev->qmr |= QSPI_QMR_MSTR;
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-
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- /*
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- * Set QCR and QWR to default values for spi flash operation.
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- * If more custom QCR and QRW are needed, overload mode variable
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- */
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- dev->qcr = (QSPI_QDR_CONT | QSPI_QDR_BITSE);
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-
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- if (!(mode & SPI_CS_HIGH))
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- dev->qwr |= QSPI_QWR_CSIV;
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-
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- return &dev->slave;
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-}
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-
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-/* Transfer 8 bit at a time */
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-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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- void *din, unsigned long flags)
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-{
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- struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
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- volatile qspi_t *qspi = dev->regs;
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- u8 *txbuf = (u8 *)dout;
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- u8 *rxbuf = (u8 *)din;
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- u32 count = DIV_ROUND_UP(bitlen, 8);
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- u32 n, i = 0;
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-
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- /* Sanitize arguments */
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- if (slave == NULL) {
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- printf("%s: NULL slave ptr\n", __func__);
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- return -1;
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- }
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-
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- if (flags & SPI_XFER_BEGIN)
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- spi_cs_activate(slave);
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-
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- /* There is something to send, lets process it. spi_xfer is also called
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- * just to toggle chip select, so bitlen of 0 is valid */
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- if (count > 0) {
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- /*
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- * NOTE: Since chip select is driven as a bit-bang-ed GPIO
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- * using spi_cs_activate() and spi_cs_deactivate(),
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- * the chip select settings inside the controller
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- * (i.e. QCR[CONT] and QWR[CSIV]) are moot. The bits are set to
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- * keep the controller settings consistent with the actual
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- * operation of the bus.
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- */
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-
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- /* Write the slave device's settings for the controller.*/
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- write_qmr(qspi, dev->qmr);
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- write_qwr(qspi, dev->qwr);
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-
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- /* Limit transfer to 16 at a time */
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- n = min(count, 16u);
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- do {
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- /* Setup queue end point */
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- write_qwr(qspi, ((read_qwr(qspi) & QSPI_QWR_ENDQP_MASK)
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- | QSPI_QWR_ENDQP((n-1))));
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-
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- /* Write Command RAM */
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- write_qar(qspi, QSPI_QAR_CMD);
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- for (i = 0; i < n; ++i)
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- write_qdr(qspi, dev->qcr);
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-
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- /* Write TxBuf, if none given, fill with ZEROes */
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- write_qar(qspi, QSPI_QAR_TRANS);
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- if (txbuf) {
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- for (i = 0; i < n; ++i)
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- write_qdr(qspi, *txbuf++);
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- } else {
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- for (i = 0; i < n; ++i)
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- write_qdr(qspi, 0);
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- }
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-
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- /* Clear QIR[SPIF] by writing a 1 to it */
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- write_qir(qspi, read_qir(qspi) | QSPI_QIR_SPIF);
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- /* Set QDLYR[SPE] to start sending */
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- write_qdlyr(qspi, read_qdlyr(qspi) | QSPI_QDLYR_SPE);
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-
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- /* Poll QIR[SPIF] for transfer completion */
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- while ((read_qir(qspi) & QSPI_QIR_SPIF) != 1)
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- udelay(1);
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-
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- /* If given read RxBuf, load data to it */
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- if (rxbuf) {
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- write_qar(qspi, QSPI_QAR_RECV);
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- for (i = 0; i < n; ++i)
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- *rxbuf++ = read_qdr(qspi);
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- }
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-
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- /* Decrement count */
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- count -= n;
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- } while (count);
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- }
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-
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- if (flags & SPI_XFER_END)
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- spi_cs_deactivate(slave);
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-
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- return 0;
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-}
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-
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-/* Each MCF CPU may have different pin assignments for chip selects. */
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-#if defined(CONFIG_M5271)
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-/* Assert chip select, val = [1|0] , dir = out, mode = GPIO */
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-void cfspi_cs_activate(uint bus, uint cs, uint cs_active_high)
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-{
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- debug("%s: bus %d cs %d cs_active_high %d\n",
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- __func__, bus, cs, cs_active_high);
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-
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- switch (cs) {
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- case 0: /* QSPI_CS[0] = PQSPI[3] */
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- if (cs_active_high)
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- mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x08);
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- else
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- mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xF7);
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-
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- mbar_writeByte(MCF_GPIO_PDDR_QSPI,
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- mbar_readByte(MCF_GPIO_PDDR_QSPI) | 0x08);
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-
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- mbar_writeByte(MCF_GPIO_PAR_QSPI,
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- mbar_readByte(MCF_GPIO_PAR_QSPI) & 0xDF);
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- break;
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- case 1: /* QSPI_CS[1] = PQSPI[4] */
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- if (cs_active_high)
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- mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x10);
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- else
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- mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xEF);
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-
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- mbar_writeByte(MCF_GPIO_PDDR_QSPI,
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- mbar_readByte(MCF_GPIO_PDDR_QSPI) | 0x10);
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-
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- mbar_writeByte(MCF_GPIO_PAR_QSPI,
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- mbar_readByte(MCF_GPIO_PAR_QSPI) & 0x3F);
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- break;
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- case 2: /* QSPI_CS[2] = PTIMER[7] */
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- if (cs_active_high)
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- mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x80);
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- else
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- mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0x7F);
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-
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- mbar_writeByte(MCF_GPIO_PDDR_TIMER,
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- mbar_readByte(MCF_GPIO_PDDR_TIMER) | 0x80);
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-
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- mbar_writeShort(MCF_GPIO_PAR_TIMER,
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- mbar_readShort(MCF_GPIO_PAR_TIMER) & 0x3FFF);
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- break;
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- case 3: /* QSPI_CS[3] = PTIMER[3] */
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- if (cs_active_high)
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- mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x08);
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- else
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- mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0xF7);
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-
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- mbar_writeByte(MCF_GPIO_PDDR_TIMER,
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- mbar_readByte(MCF_GPIO_PDDR_TIMER) | 0x08);
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-
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- mbar_writeShort(MCF_GPIO_PAR_TIMER,
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- mbar_readShort(MCF_GPIO_PAR_TIMER) & 0xFF3F);
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- break;
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- }
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-}
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-
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-/* Deassert chip select, val = [1|0], dir = in, mode = GPIO
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- * direction set as IN to undrive the pin, external pullup/pulldown will bring
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- * bus to deassert state.
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- */
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-void cfspi_cs_deactivate(uint bus, uint cs, uint cs_active_high)
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-{
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- debug("%s: bus %d cs %d cs_active_high %d\n",
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- __func__, bus, cs, cs_active_high);
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-
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- switch (cs) {
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- case 0: /* QSPI_CS[0] = PQSPI[3] */
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- if (cs_active_high)
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- mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xF7);
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- else
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- mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x08);
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-
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- mbar_writeByte(MCF_GPIO_PDDR_QSPI,
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- mbar_readByte(MCF_GPIO_PDDR_QSPI) & 0xF7);
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-
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- mbar_writeByte(MCF_GPIO_PAR_QSPI,
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- mbar_readByte(MCF_GPIO_PAR_QSPI) & 0xDF);
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- break;
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- case 1: /* QSPI_CS[1] = PQSPI[4] */
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- if (cs_active_high)
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- mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xEF);
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- else
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- mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x10);
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-
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- mbar_writeByte(MCF_GPIO_PDDR_QSPI,
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- mbar_readByte(MCF_GPIO_PDDR_QSPI) & 0xEF);
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-
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- mbar_writeByte(MCF_GPIO_PAR_QSPI,
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- mbar_readByte(MCF_GPIO_PAR_QSPI) & 0x3F);
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- break;
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- case 2: /* QSPI_CS[2] = PTIMER[7] */
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- if (cs_active_high)
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- mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0x7F);
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- else
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- mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x80);
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-
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- mbar_writeByte(MCF_GPIO_PDDR_TIMER,
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- mbar_readByte(MCF_GPIO_PDDR_TIMER) & 0x7F);
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-
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- mbar_writeShort(MCF_GPIO_PAR_TIMER,
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- mbar_readShort(MCF_GPIO_PAR_TIMER) & 0x3FFF);
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- break;
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- case 3: /* QSPI_CS[3] = PTIMER[3] */
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- if (cs_active_high)
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- mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0xF7);
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- else
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- mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x08);
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-
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- mbar_writeByte(MCF_GPIO_PDDR_TIMER,
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- mbar_readByte(MCF_GPIO_PDDR_TIMER) & 0xF7);
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-
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- mbar_writeShort(MCF_GPIO_PAR_TIMER,
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- mbar_readShort(MCF_GPIO_PAR_TIMER) & 0xFF3F);
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- break;
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- }
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-}
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-#endif /* CONFIG_M5271 */
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Tom Rini