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@@ -5,14 +5,14 @@
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*/
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/*
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- * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
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+ * Generic driver for Freescale DDR/DDR2/DDR3/DDR4 memory controller.
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* Based on code from spd_sdram.c
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* Author: James Yang [at freescale.com]
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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-
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+#include <fsl_errata.h>
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#include <fsl_ddr.h>
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#include <fsl_immap.h>
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#include <asm/io.h>
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@@ -2306,6 +2306,38 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
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unsigned int ip_rev = 0;
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unsigned int unq_mrs_en = 0;
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int cs_en = 1;
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+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
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+ unsigned int ddr_freq;
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+#endif
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+#if (defined(CONFIG_SYS_FSL_ERRATUM_A008378) && \
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+ defined(CONFIG_SYS_FSL_DDRC_GEN4)) || \
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+ defined(CONFIG_SYS_FSL_ERRATUM_A009942)
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+ struct ccsr_ddr __iomem *ddrc;
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+
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+ switch (ctrl_num) {
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+ case 0:
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+ ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR;
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+ break;
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+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
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+ case 1:
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+ ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
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+ break;
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+#endif
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+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
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+ case 2:
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+ ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
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+ break;
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+#endif
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+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
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+ case 3:
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+ ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
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+ break;
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+#endif
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+ default:
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+ printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
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+ return 1;
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+ }
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+#endif
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memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
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@@ -2526,5 +2558,105 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
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ddr->debug[2] |= 0x00000200; /* set bit 22 */
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#endif
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+#if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4)
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+ /* Erratum applies when accumulated ECC is used, or DBI is enabled */
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+#define IS_ACC_ECC_EN(v) ((v) & 0x4)
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+#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
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+ if (has_erratum_a008378()) {
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+ if (IS_ACC_ECC_EN(ddr->ddr_sdram_cfg) ||
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+ IS_DBI(ddr->ddr_sdram_cfg_3)) {
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+ ddr->debug[28] = ddr_in32(&ddrc->debug[28]);
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+ ddr->debug[28] |= (0x9 << 20);
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+ }
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+ }
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+#endif
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+
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+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
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+ ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
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+ ddr->debug[28] |= ddr_in32(&ddrc->debug[28]);
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+ ddr->debug[28] &= 0xff0fff00;
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+ if (ddr_freq <= 1333)
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+ ddr->debug[28] |= 0x0080006a;
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+ else if (ddr_freq <= 1600)
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+ ddr->debug[28] |= 0x0070006f;
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+ else if (ddr_freq <= 1867)
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+ ddr->debug[28] |= 0x00700076;
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+ else if (ddr_freq <= 2133)
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+ ddr->debug[28] |= 0x0060007b;
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+ if (popts->cpo_sample)
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+ ddr->debug[28] = (ddr->debug[28] & 0xffffff00) |
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+ popts->cpo_sample;
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+#endif
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+
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return check_fsl_memctl_config_regs(ddr);
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}
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+
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+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
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+/*
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+ * This additional workaround of A009942 checks the condition to determine if
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+ * the CPO value set by the existing A009942 workaround needs to be updated.
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+ * If need, print a warning to prompt user reconfigure DDR debug_29[24:31] with
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+ * expected optimal value, the optimal value is highly board dependent.
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+ */
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+void erratum_a009942_check_cpo(void)
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+{
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+ struct ccsr_ddr __iomem *ddr =
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+ (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
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+ u32 cpo, cpo_e, cpo_o, cpo_target, cpo_optimal;
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+ u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24;
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+ u32 cpo_max = cpo_min;
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+ u32 sdram_cfg, i, tmp, lanes, ddr_type;
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+ bool update_cpo = false, has_ecc = false;
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+
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+ sdram_cfg = ddr_in32(&ddr->sdram_cfg);
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+ if (sdram_cfg & SDRAM_CFG_32_BE)
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+ lanes = 4;
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+ else if (sdram_cfg & SDRAM_CFG_16_BE)
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+ lanes = 2;
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+ else
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+ lanes = 8;
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+
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+ if (sdram_cfg & SDRAM_CFG_ECC_EN)
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+ has_ecc = true;
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+
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+ /* determine the maximum and minimum CPO values */
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+ for (i = 9; i < 9 + lanes / 2; i++) {
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+ cpo = ddr_in32(&ddr->debug[i]);
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+ cpo_e = cpo >> 24;
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+ cpo_o = (cpo >> 8) & 0xff;
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+ tmp = min(cpo_e, cpo_o);
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+ if (tmp < cpo_min)
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+ cpo_min = tmp;
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+ tmp = max(cpo_e, cpo_o);
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+ if (tmp > cpo_max)
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+ cpo_max = tmp;
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+ }
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+
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+ if (has_ecc) {
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+ cpo = ddr_in32(&ddr->debug[13]);
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+ cpo = cpo >> 24;
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+ if (cpo < cpo_min)
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+ cpo_min = cpo;
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+ if (cpo > cpo_max)
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+ cpo_max = cpo;
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+ }
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+
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+ cpo_target = ddr_in32(&ddr->debug[28]) & 0xff;
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+ cpo_optimal = ((cpo_max + cpo_min) >> 1) + 0x27;
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+ debug("cpo_optimal = 0x%x, cpo_target = 0x%x\n", cpo_optimal,
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+ cpo_target);
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+ debug("cpo_max = 0x%x, cpo_min = 0x%x\n", cpo_max, cpo_min);
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+
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+ ddr_type = (sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
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+ SDRAM_CFG_SDRAM_TYPE_SHIFT;
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+ if (ddr_type == SDRAM_TYPE_DDR4)
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+ update_cpo = (cpo_min + 0x3b) < cpo_target ? true : false;
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+ else if (ddr_type == SDRAM_TYPE_DDR3)
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+ update_cpo = (cpo_min + 0x3f) < cpo_target ? true : false;
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+
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+ if (update_cpo) {
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+ printf("WARN: pls set popts->cpo_sample = 0x%x ", cpo_optimal);
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+ printf("in <board>/ddr.c to optimize cpo\n");
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+ }
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+}
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+#endif
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Shengzhou Liu