arm: mvebu: correct comments around cas_wl/cas_l

The order of members in struct hws_topology_map is cas_wl, cas_l. The
comments in the original db-88f6820-gp.c had this wrong and have been
copied to other Armada-385 based boards. Practically this hasn't made a
difference since all these boards set both cas_wl and cas_l to 0
(autodetect) but if there were ever a board that did need to set these
explicitly they would run into unexpected issued.

Update the comments to reflect the correct order of structure members.

Reported-by: Tobi Wulff <tobi.wulff@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>

board/CZ.NIC/turris_omnia/turris_omnia.c

@@ -212,7 +212,7 @@ static struct hws_topology_map board_topology_map_1g = {
 	    BUS_WIDTH_16,		/* memory_width */
 	    MEM_4G,			/* mem_size */
 	    DDR_FREQ_800,		/* frequency */
-	    0, 0,			/* cas_l cas_wl */
+	    0, 0,			/* cas_wl cas_l */
 	    HWS_TEMP_NORMAL,		/* temperature */
 	    HWS_TIM_2T} },		/* timing (force 2t) */
 	5,				/* Num Of Bus Per Interface*/
@@ -231,7 +231,7 @@ static struct hws_topology_map board_topology_map_2g = {
 	    BUS_WIDTH_16,		/* memory_width */
 	    MEM_8G,			/* mem_size */
 	    DDR_FREQ_800,		/* frequency */
-	    0, 0,			/* cas_l cas_wl */
+	    0, 0,			/* cas_wl cas_l */
 	    HWS_TEMP_NORMAL,		/* temperature */
 	    HWS_TIM_2T} },		/* timing (force 2t) */
 	5,				/* Num Of Bus Per Interface*/

board/Marvell/db-88f6820-amc/db-88f6820-amc.c

@@ -68,7 +68,7 @@ static struct hws_topology_map board_topology_map = {
 	    BUS_WIDTH_8,		/* memory_width */
 	    MEM_2G,			/* mem_size */
 	    DDR_FREQ_800,		/* frequency */
-	    0, 0,			/* cas_l cas_wl */
+	    0, 0,			/* cas_wl cas_l */
 	    HWS_TEMP_LOW,		/* temperature */
 	    HWS_TIM_DEFAULT} },		/* timing */
 	5,				/* Num Of Bus Per Interface*/

board/Marvell/db-88f6820-gp/db-88f6820-gp.c

@@ -89,7 +89,7 @@ static struct hws_topology_map board_topology_map = {
 	    BUS_WIDTH_8,		/* memory_width */
 	    MEM_4G,			/* mem_size */
 	    DDR_FREQ_800,		/* frequency */
-	    0, 0,			/* cas_l cas_wl */
+	    0, 0,			/* cas_wl cas_l */
 	    HWS_TEMP_LOW,		/* temperature */
 	    HWS_TIM_DEFAULT} },		/* timing */
 	5,				/* Num Of Bus Per Interface*/

board/gdsys/a38x/controlcenterdc.c

@@ -52,7 +52,7 @@ static struct hws_topology_map ddr_topology_map = {
 	    BUS_WIDTH_16,		/* memory_width */
 	    MEM_4G,			/* mem_size */
 	    DDR_FREQ_533,		/* frequency */
-	    0, 0,			/* cas_l cas_wl */
+	    0, 0,			/* cas_wl cas_l */
 	    HWS_TEMP_LOW,		/* temperature */
 	    HWS_TIM_DEFAULT} },		/* timing */
 	5,				/* Num Of Bus Per Interface*/

board/solidrun/clearfog/clearfog.c

@@ -82,7 +82,7 @@ static struct hws_topology_map board_topology_map = {
 	    BUS_WIDTH_16,		/* memory_width */
 	    MEM_4G,			/* mem_size */
 	    DDR_FREQ_800,		/* frequency */
-	    0, 0,			/* cas_l cas_wl */
+	    0, 0,			/* cas_wl cas_l */
 	    HWS_TEMP_LOW,		/* temperature */
 	    HWS_TIM_DEFAULT} },		/* timing */
 	5,				/* Num Of Bus Per Interface*/