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@@ -40,7 +40,7 @@ enum clk_ids {
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MOD_CLK_BASE
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};
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-static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
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+static const struct cpg_core_clk r8a7794_core_clks[] = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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DEF_INPUT("usb_extal", CLK_USB_EXTAL),
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@@ -85,7 +85,7 @@ static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
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DEF_DIV6P1("mmc0", R8A7794_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
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};
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-static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
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+static const struct mssr_mod_clk r8a7794_mod_clks[] = {
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DEF_MOD("msiof0", 0, R8A7794_CLK_MP),
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DEF_MOD("vcp0", 101, R8A7794_CLK_ZS),
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DEF_MOD("vpc0", 103, R8A7794_CLK_ZS),
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@@ -188,10 +188,6 @@ static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
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DEF_MOD("scifa5", 1108, R8A7794_CLK_MP),
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};
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-static const unsigned int r8a7794_crit_mod_clks[] __initconst = {
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- MOD_CLK_ID(408), /* INTC-SYS (GIC) */
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-};
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-
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/*
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* CPG Clock Data
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*/
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@@ -210,7 +206,7 @@ static const unsigned int r8a7794_crit_mod_clks[] __initconst = {
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*/
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#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
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(((md) & BIT(13)) >> 13))
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-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = {
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+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] = {
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{ 1, 208, 88, 200 },
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{ 1, 156, 66, 150 },
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{ 2, 240, 102, 230 },
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