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@@ -1,6 +1,9 @@
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/*
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* Copyright 2006,2009 Freescale Semiconductor, Inc.
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*
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+ * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
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+ * Changes for multibus/multiadapter I2C support.
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+ *
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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@@ -17,12 +20,8 @@
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*/
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#include <common.h>
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-
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-#ifdef CONFIG_HARD_I2C
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-
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#include <command.h>
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#include <i2c.h> /* Functional interface */
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-
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#include <asm/io.h>
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#include <asm/fsl_i2c.h> /* HW definitions */
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@@ -47,25 +46,10 @@
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DECLARE_GLOBAL_DATA_PTR;
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-/* Initialize the bus pointer to whatever one the SPD EEPROM is on.
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- * Default is bus 0. This is necessary because the DDR initialization
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- * runs from ROM, and we can't switch buses because we can't modify
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- * the global variables.
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- */
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-#ifndef CONFIG_SYS_SPD_BUS_NUM
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-#define CONFIG_SYS_SPD_BUS_NUM 0
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-#endif
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-static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM;
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-#if defined(CONFIG_I2C_MUX)
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-static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0;
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-#endif
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-
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-static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED};
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-
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static const struct fsl_i2c *i2c_dev[2] = {
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- (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET),
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-#ifdef CONFIG_SYS_I2C2_OFFSET
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- (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET)
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+ (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
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+#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
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+ (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET)
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#endif
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};
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@@ -222,12 +206,9 @@ static unsigned int get_i2c_clock(int bus)
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return gd->arch.i2c1_clk; /* I2C1 clock */
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}
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-void
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-i2c_init(int speed, int slaveadd)
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+static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
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{
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const struct fsl_i2c *dev;
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- unsigned int temp;
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- int bus_num, i;
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#ifdef CONFIG_SYS_I2C_INIT_BOARD
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/* Call board specific i2c bus reset routine before accessing the
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@@ -236,23 +217,14 @@ i2c_init(int speed, int slaveadd)
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*/
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i2c_init_board();
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#endif
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-#ifdef CONFIG_SYS_I2C2_OFFSET
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- bus_num = 2;
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-#else
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- bus_num = 1;
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-#endif
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- for (i = 0; i < bus_num; i++) {
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- dev = i2c_dev[i];
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-
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- writeb(0, &dev->cr); /* stop I2C controller */
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- udelay(5); /* let it shutdown in peace */
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- temp = set_i2c_bus_speed(dev, get_i2c_clock(i), speed);
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- if (gd->flags & GD_FLG_RELOC)
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- i2c_bus_speed[i] = temp;
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- writeb(slaveadd << 1, &dev->adr);/* write slave address */
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- writeb(0x0, &dev->sr); /* clear status register */
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- writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
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- }
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+ dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
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+
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+ writeb(0, &dev->cr); /* stop I2C controller */
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+ udelay(5); /* let it shutdown in peace */
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+ set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
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+ writeb(slaveadd << 1, &dev->adr);/* write slave address */
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+ writeb(0x0, &dev->sr); /* clear status register */
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+ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
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#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
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/* Call board specific i2c bus reset routine AFTER the bus has been
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@@ -265,12 +237,13 @@ i2c_init(int speed, int slaveadd)
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}
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static int
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-i2c_wait4bus(void)
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+i2c_wait4bus(struct i2c_adapter *adap)
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{
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+ struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
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unsigned long long timeval = get_ticks();
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const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
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- while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) {
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+ while (readb(&dev->sr) & I2C_SR_MBB) {
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if ((get_ticks() - timeval) > timeout)
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return -1;
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}
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@@ -279,20 +252,21 @@ i2c_wait4bus(void)
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}
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static __inline__ int
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-i2c_wait(int write)
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+i2c_wait(struct i2c_adapter *adap, int write)
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{
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u32 csr;
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unsigned long long timeval = get_ticks();
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const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
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+ struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
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do {
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- csr = readb(&i2c_dev[i2c_bus_num]->sr);
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+ csr = readb(&dev->sr);
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if (!(csr & I2C_SR_MIF))
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continue;
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/* Read again to allow register to stabilise */
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- csr = readb(&i2c_dev[i2c_bus_num]->sr);
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+ csr = readb(&dev->sr);
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- writeb(0x0, &i2c_dev[i2c_bus_num]->sr);
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+ writeb(0x0, &dev->sr);
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if (csr & I2C_SR_MAL) {
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debug("i2c_wait: MAL\n");
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@@ -317,29 +291,32 @@ i2c_wait(int write)
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}
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static __inline__ int
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-i2c_write_addr (u8 dev, u8 dir, int rsta)
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+i2c_write_addr(struct i2c_adapter *adap, u8 dev, u8 dir, int rsta)
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{
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+ struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
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+
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writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
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| (rsta ? I2C_CR_RSTA : 0),
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- &i2c_dev[i2c_bus_num]->cr);
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+ &device->cr);
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- writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr);
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+ writeb((dev << 1) | dir, &device->dr);
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- if (i2c_wait(I2C_WRITE_BIT) < 0)
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+ if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
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return 0;
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return 1;
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}
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static __inline__ int
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-__i2c_write(u8 *data, int length)
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+__i2c_write(struct i2c_adapter *adap, u8 *data, int length)
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{
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+ struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
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int i;
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for (i = 0; i < length; i++) {
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- writeb(data[i], &i2c_dev[i2c_bus_num]->dr);
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+ writeb(data[i], &dev->dr);
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- if (i2c_wait(I2C_WRITE_BIT) < 0)
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+ if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
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break;
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}
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@@ -347,57 +324,60 @@ __i2c_write(u8 *data, int length)
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}
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static __inline__ int
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-__i2c_read(u8 *data, int length)
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+__i2c_read(struct i2c_adapter *adap, u8 *data, int length)
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{
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+ struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
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int i;
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writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
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- &i2c_dev[i2c_bus_num]->cr);
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+ &dev->cr);
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/* dummy read */
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- readb(&i2c_dev[i2c_bus_num]->dr);
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+ readb(&dev->dr);
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for (i = 0; i < length; i++) {
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- if (i2c_wait(I2C_READ_BIT) < 0)
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+ if (i2c_wait(adap, I2C_READ_BIT) < 0)
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break;
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/* Generate ack on last next to last byte */
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if (i == length - 2)
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writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
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- &i2c_dev[i2c_bus_num]->cr);
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+ &dev->cr);
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/* Do not generate stop on last byte */
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if (i == length - 1)
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writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
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- &i2c_dev[i2c_bus_num]->cr);
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+ &dev->cr);
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- data[i] = readb(&i2c_dev[i2c_bus_num]->dr);
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+ data[i] = readb(&dev->dr);
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}
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return i;
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}
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-int
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-i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
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+static int
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+fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data,
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+ int length)
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{
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+ struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
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int i = -1; /* signal error */
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u8 *a = (u8*)&addr;
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- if (i2c_wait4bus() < 0)
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+ if (i2c_wait4bus(adap) < 0)
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return -1;
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if ((!length || alen > 0)
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- && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
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- && __i2c_write(&a[4 - alen], alen) == alen)
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+ && i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0
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+ && __i2c_write(adap, &a[4 - alen], alen) == alen)
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i = 0; /* No error so far */
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if (length &&
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- i2c_write_addr(dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
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- i = __i2c_read(data, length);
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+ i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
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+ i = __i2c_read(adap, data, length);
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- writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
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+ writeb(I2C_CR_MEN, &device->cr);
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- if (i2c_wait4bus()) /* Wait until STOP */
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+ if (i2c_wait4bus(adap)) /* Wait until STOP */
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debug("i2c_read: wait4bus timed out\n");
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if (i == length)
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@@ -406,20 +386,22 @@ i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
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return -1;
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}
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-int
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-i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
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+static int
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+fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen,
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+ u8 *data, int length)
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{
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+ struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
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int i = -1; /* signal error */
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u8 *a = (u8*)&addr;
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- if (i2c_wait4bus() >= 0
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- && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
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- && __i2c_write(&a[4 - alen], alen) == alen) {
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- i = __i2c_write(data, length);
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+ if (i2c_wait4bus(adap) >= 0 &&
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+ i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&
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+ __i2c_write(adap, &a[4 - alen], alen) == alen) {
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+ i = __i2c_write(adap, data, length);
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}
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- writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
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- if (i2c_wait4bus()) /* Wait until STOP */
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+ writeb(I2C_CR_MEN, &device->cr);
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+ if (i2c_wait4bus(adap)) /* Wait until STOP */
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debug("i2c_write: wait4bus timed out\n");
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if (i == length)
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@@ -428,72 +410,42 @@ i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
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return -1;
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}
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-int
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-i2c_probe(uchar chip)
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+static int
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+fsl_i2c_probe(struct i2c_adapter *adap, uchar chip)
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{
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+ struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
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/* For unknow reason the controller will ACK when
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* probing for a slave with the same address, so skip
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* it.
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*/
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- if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1))
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- return -1;
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-
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- return i2c_read(chip, 0, 0, NULL, 0);
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-}
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-
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-int i2c_set_bus_num(unsigned int bus)
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-{
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-#if defined(CONFIG_I2C_MUX)
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- if (bus < CONFIG_SYS_MAX_I2C_BUS) {
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- i2c_bus_num = bus;
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- } else {
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- int ret;
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-
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- ret = i2x_mux_select_mux(bus);
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- if (ret)
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- return ret;
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- i2c_bus_num = 0;
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- }
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- i2c_bus_num_mux = bus;
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-#else
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-#ifdef CONFIG_SYS_I2C2_OFFSET
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- if (bus > 1) {
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-#else
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- if (bus > 0) {
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-#endif
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+ if (chip == (readb(&dev->adr) >> 1))
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return -1;
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- }
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- i2c_bus_num = bus;
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-#endif
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- return 0;
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+ return fsl_i2c_read(adap, chip, 0, 0, NULL, 0);
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}
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-int i2c_set_bus_speed(unsigned int speed)
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+static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
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+ unsigned int speed)
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{
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- unsigned int i2c_clk = (i2c_bus_num == 1)
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- ? gd->arch.i2c2_clk : gd->arch.i2c1_clk;
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+ struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
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- writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */
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- i2c_bus_speed[i2c_bus_num] =
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- set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed);
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- writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */
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+ writeb(0, &dev->cr); /* stop controller */
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+ set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
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+ writeb(I2C_CR_MEN, &dev->cr); /* start controller */
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return 0;
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}
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-unsigned int i2c_get_bus_num(void)
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-{
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-#if defined(CONFIG_I2C_MUX)
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- return i2c_bus_num_mux;
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-#else
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- return i2c_bus_num;
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+/*
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+ * Register fsl i2c adapters
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+ */
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+U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
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+ fsl_i2c_write, fsl_i2c_set_bus_speed,
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+ CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
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|
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+ 0)
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|
|
+#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
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|
|
+U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
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|
|
+ fsl_i2c_write, fsl_i2c_set_bus_speed,
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|
|
+ CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
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|
|
+ 1)
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|
|
#endif
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|
|
-}
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|
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-
|
|
|
-unsigned int i2c_get_bus_speed(void)
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|
|
-{
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|
|
- return i2c_bus_speed[i2c_bus_num];
|
|
|
-}
|
|
|
-
|
|
|
-#endif /* CONFIG_HARD_I2C */
|