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@@ -30,6 +30,11 @@
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#endif /* CONFIG_MX6Q */
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#endif /* CONFIG_MX6Q */
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#else
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#else
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+enum {
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+ DDR_TYPE_DDR3,
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+ DDR_TYPE_LPDDR2,
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+};
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+
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/* MMDC P0/P1 Registers */
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/* MMDC P0/P1 Registers */
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struct mmdc_p_regs {
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struct mmdc_p_regs {
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u32 mdctl;
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u32 mdctl;
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@@ -387,6 +392,7 @@ struct mx6_ddr_sysinfo {
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u8 rst_to_cke; /* Time from SDE enable to CKE rise */
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u8 rst_to_cke; /* Time from SDE enable to CKE rise */
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u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */
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u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */
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u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
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u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
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+ u8 ddr_type; /* DDR type: DDR3(0) or LPDDR2(1) */
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};
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};
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/*
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/*
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